Skip to main content
SpringerLink
Log in
SpringerLink
Log in

Nanoscale Application-Specific Integrated Circuits

  • Chapter
  • First Online:
Nanoelectronic Circuit Design

Abstract

This chapter provides an overview of the nanoscale application-specific integrated circuit (NASIC) fabric. The NASIC fabric has spawned several research directions by multiple groups. This overview is a snapshot of the thinking, techniques, and some of the results to date. NASIC is targeted as a CMOS-replacement technology. The project encompasses aspects from the physical layer and manufacturing techniques, to devices, circuits, and architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    A new derivative of NASICs is MagNASIC/Spin Wave Function (SPWF) that follows magnetic physical phenomena instead of charge-based electronics. 3D NASIC is a NASIC fabric that is based on conventional (CMOS-like) 3D integration combined with nanowire VLSI. A number of other devices than presented here are based on depletion-mode xnwFETs. These and NASIC memories are not discussed in this chapter; relevant papers can be found from the authors’ websites.

  2. 2.

    The use of separate precharge and evaluate signals for successive stages also implies that signal monotonicity issues prevalent in conventional dynamic circuits (that typically require either domino logic, i.e., insertion of a static inverter between dynamic stages or np-CMOS type circuit styles) do not affect NASIC dynamic circuits.

  3. 3.

    A note on regression-based vs. analytical modeling: A regression based approach is very generic and can be used to fit arbitrary device characteristics. Coefficients extracted from regression data fits are representative of the device behavior over sweeps of drain-source and gate-source voltages. This is in contrast to conventional in-built models in SPICE for MOSFETs and other devices, which use analytical equations derived from theory and physical parameters, such as channel length and width. The regression coefficients in our approach may not directly correspond to conventional physical parameters. Therefore, different regression fits will need to be extracted for devices with varying geometries, doping, etc.

References

  1. C. P. Collier, E. W. Wong, M. Belohradský, F. M. Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams, and J. R. Heath, Electronically configurable molecular-based logic gates, Science, vol. 285, pp. 391–394, 1999.

    Article  Google Scholar 

  2. K. Galatsis, K. Wang, Y. Botros, Y. Yang, Y-H. Xie, J. Stoddart, R. Kaner, C. Ozhan, J. Liu, M. Ozkan, C. Zhou, and K. W. Kim, Emerging memory devices, IEEE Circ. Dev. Mag., vol. 22, pp. 12–21, 2006.

    Article  Google Scholar 

  3. W. Lu and C. M. Lieber, Semiconductor nanowires, J. Phys. D Appl. Phys., vol. 39, pp. R387–R406, 2006.

    Article  Google Scholar 

  4. Y. Cui, X. Duan, J. Hu, and C. M. Lieber, Doping and electrical transport in silicon nanowires, J. Phys. Chem. B, vol. 104, pp. 5213–5216, 2000.

    Article  Google Scholar 

  5. A. B. Greytak, L. J. Lauhon, M. S. Gudiksen, and C. M. Lieber, Growth and transport properties of complementary germanium nanowire field-effect transistors, Appl. Phys. Lett., vol. 84, pp. 4176–4178, 2004.

    Article  Google Scholar 

  6. J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, Ge/Si nanowire heterostructures as high-performance field-effect transistor, Nature, vol. 441, pp. 489–493, 2006.

    Article  Google Scholar 

  7. M. I. Khan, X. Wang, K. N. Bozhilov, and C. S. Ozkan, Templated fabrication of InSb nanowires for nanoelectronics, J. Nanomater., vol. 2008, pp. 1–5, 2008.

    Article  Google Scholar 

  8. Y. Li, G. W. Meng, L. D. Zhang, and F. Phillipp, Ordered semiconductor ZnO nanowire arrays and their photoluminescence properties, Appl. Phys. Lett., vol. 76, pp. 2011–2013, 2000.

    Article  Google Scholar 

  9. X. Duan, Y. Huang, Y. Cui, J. Wang, and C. M. Lieber, Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices, Nature, vol. 409, pp. 66–69, 2001.

    Article  Google Scholar 

  10. Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K-Y. Kim, and C. M. Lieber, Logic gates and computation from assembled nanowire building blocks, Science, vol. 294, no. 5545, pp. 1313–1317, 2001.

    Article  Google Scholar 

  11. Y. Wu, J. Xiang, C. Yang, W. Lu, and C. M. Lieber, Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures, Nature, vol. 430, pp. 61–65, 2004.

    Article  Google Scholar 

  12. Semiconductor Nanowires: Fabrication, Physical Properties and Applications, Warrendale, PA: Materials Research Society, 2006.

    Google Scholar 

  13. Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath, and C. M. Lieber, Nanowire crossbar arrays as address decoders for integrated nanosystems, Science, vol. 302, pp. 1377–1379, 2003.

    Article  Google Scholar 

  14. D. Wang, B. Sheriff, M. McAlpine, and J. Heath, Development of ultra-high density silicon nanowire arrays for electronics applications, Nano Res., vol. 1, pp. 9–21, 2008.

    Article  Google Scholar 

  15. Sentaurus Device User Guide, Synopsys, Inc., 2007.

    Google Scholar 

  16. A. Marchi, E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs, Solid State Electron, vol. 50, pp. 78–85, 2006.

    Article  Google Scholar 

  17. S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, K. H. Cho, I. K. Ku, H. Cho, W-J. Jang, D-W. Kim, D. Park, and W-S. Lee, Investigation of nanowire size dependency on TSNWFET, in Proc. IEEE Electron Devices Meeting, pp. 891–894, 2007.

    Google Scholar 

  18. P. Stolk, F. Widdershoven, and D. Klaassen, Modeling statistical dopant fluctuations in MOS transistors, IEEE Trans. Electron Devices, vol. 45, pp. 1960–1971, 1998.

    Article  Google Scholar 

  19. P. Narayanan, M. Leuchtenburg, T. Wang, and C. A. Moritz, CMOS control enabled single-type FET NASIC, in Proc. IEEE Int. Symp. on VLSI, April 2008.

    Google Scholar 

  20. P. Narayanan, K. W. Park, C. O. Chui, and C. A. Moritz, Validating cascading of crossbar circuits with an integrated device-circuit exploration, in Proc. IEEE/ACM Symposium on Nanoscale Architectures, San Francisco, CA, 2009.

    Google Scholar 

  21. HSPICE User’s Manual, Campbell, CA: Meta-Software, Inc., 1992.

    Google Scholar 

  22. T. Wang, P. Narayanan, and C. A. Moritz, Heterogeneous 2-level logic and its density and fault tolerance implications in nanoscale fabrics, IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 22–30, 2009.

    Article  Google Scholar 

  23. C. A. Moritz, T. Wang, P. Narayanan, M. Leuchtenburg, Y. Guo, C. Dezan, and M. Bennaser, Fault-tolerant nanoscale processors on semiconductor nanowire grids, IEEE Trans. Circ. Syst. I Special Issue on Nanoelectronic Circuits and Nanoarchitectures, vol. 54, no. 11, pp. 2422–2437, 2007.

    Google Scholar 

  24. T. Wang, P. Narayanan, and C. A. Moritz, Combining 2-level logic families in grid-based nanoscale fabrics, in Proc. IEEE/ACM Symposium on Nanoscale Architectures, San Jose, CA, Oct. 2007.

    Google Scholar 

  25. M. Sindhwani, T. Srikanthan, and K. V. Asari, VLSI efficient discrete-time cellular neural network processor, IEEE Proc. Circuits Devices Syst., vol. 149, pp. 167–171, 2002.

    Article  Google Scholar 

  26. L. O. Chua and L. Yang, Cellular neural networks: theory, IEEE Trans. Circuits Syst. I, vol. 35, pp. 1257–1272, 1988.

    Article  MATH  MathSciNet  Google Scholar 

  27. P. Narayanan, T. Wang, M. Leuchtenburg, and C. A. Moritz, Comparison of analog and digital nanoscale systems: issues for the nano-architect, in Proc. IEEE Nanoelectronics Conference, March 2008.

    Google Scholar 

  28. P. Narayanan, T. Wang, and C. A. Moritz, Programmable cellular architectures at the nanoscale, unpublished manuscript.

    Google Scholar 

  29. International Technology Roadmap for Semiconductors, 2007 edition. Available online at http://public.itrs.net/

  30. A. A. Bruen and M. A. Forcinito, Cryptography, Information Theory, and Error-Correction, New York: Wiley-Interscience, 2005.

    Google Scholar 

  31. I. L. Sayers and D. J. Kinniment, Low-cost residue codes and their applications to self-checking VLSI systems, IEEE Proc., vol. 132, Pt. E, no. 4, 1985.

    Google Scholar 

  32. H. Krishna and J. D. Sun, On theory and fast algorithms for error correction in residue number system product codes, IEEE Trans. Comput., vol. 42, no. 7, 1993.

    Google Scholar 

  33. W. H. Pierce, Interconnection Structure for Redundant Logic, Failure-Tolerant Computer Design, New York: Academic Press, 1965.

    Google Scholar 

  34. R. E. Lyions and W. Vanderkulk, The use of triple modular redundancy to improve computer reliability, IBM J. Res. Develop. vol. 6, no. 2, 1962.

    Google Scholar 

  35. R. C. Rose and D. K. Ray-Chaudhuri, On a class of error-correcting binary group codes, Info. Control, vol. 3, pp. 68–79, March 1960.

    Article  Google Scholar 

  36. A. Hocquengham, Codes correcteurs d’erreurs, Chiffre, vol. 2, pp. 147–156, 1959.

    Google Scholar 

  37. T. R. N. Rao, Error Coding for Arithmetic Processor, New York: Academic Press, 1974.

    Google Scholar 

  38. B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Reading, MA: Addison-Wesley, 1989.

    Google Scholar 

  39. D. B. Armstrong, A general method of applying error correction to synchronous digital systems, Bell Syst. Tech. J., vol. 40, pp. 477–593, 1961.

    Google Scholar 

  40. A. DeHon. Nanowire-based programmable architectures, ACM J. Emerg. Tech.. Comput. Syst., vol. 1, pp. 109–162, 2005.

    Article  Google Scholar 

  41. K. K. Likharev and D. B. Strukov, CMOL: devices, circuits, and architectures. Introducing molecular electronics, G. F. G. Cuniberti and K. Richter (eds.), 2005.

    Google Scholar 

  42. D. B. Strukov and K. K. Likharev, Reconfigurable hybrid CMOS devices for image processing, IEEE Trans. Nanotechnol, vol. 6, pp. 696–710, 2007.

    Article  Google Scholar 

  43. G. S. Snider and R. S. Williams, Nano/CMOS architectures using a field-programmable nanowire interconnect, Nanotechnology, vol. 18, pp. 1–11, 2007.

    Google Scholar 

  44. Y. Li, F. Qian, J. Xiang, and C. M. Lieber, Nanowire electronic and optoelectronic devices, Mater. Today, vol. 9, pp. 18–27, 2006.

    Article  Google Scholar 

  45. M. Bennaser, Y. Guo, and C. A. Moritz, Designing memory subsystems resilient to process variations, in Proc. Annual Symposium on VLSI, pp. 357–363, Porto Alegre, Brazil, March 2007.

    Google Scholar 

  46. D. Burnett, K. Erington, C. Subramanian, and K. Baker, Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits, in Proc. Symposium on VLSI Technology, pp. 14–15, June 1994.

    Google Scholar 

  47. E. Humenay, D. Tarjan, and K. Skadron, Impact of parameter variations on multi-core chips, in Proc. Workshop on Architecture Support for Gigascale Integration, June 2006.

    Google Scholar 

  48. A. Agarwal, B. Paul, H. Mahmoodi, A. Datta, and K. Roy, A process-tolerant cache architecture for improved yield in nanoscale technologies, IEEE Trans. VLSI Syst., vol. 13, no. 1, pp. 27–38, Jan. 2005.

    Article  Google Scholar 

  49. X. Tang, V. K. De, and J. D. Meindl, Intrinsic MOSFET parameter fluctuations due to random dopant placement, IEEE Trans. VLSI Syst., vol. 5, no. 4, pp. 369–376, Dec. 1997.

    Article  Google Scholar 

  50. E. Garnett, W. Liang, and P. Yang, Growth and electrical characteristics of platinum-nano-particle-catalyzed silicon nanowires, Adv. Mater., vol. 19, pp. 2946–2950, 2007.

    Article  Google Scholar 

  51. Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, High-performance silicon nanowire field effect transistors, Nano Lett., vol. 3, no. 2, pp. 149–152, 2003.

    Article  Google Scholar 

  52. J. Kim, D. H. Shin, E. Lee, and C. Han, Electrical characteristics of singly and doubly connected Ni Silicide nanowire grown by plasma-enhanced chemical vapor deposition, Appl. Phys. Lett., vol. 90, p. 253103, 2007.

    Article  Google Scholar 

  53. M. Leuchtenburg, P. Narayanan, T. Wang, and C. A. Moritz, Process variation and 2-way redundancy in grid-based nanoscale processors, in Proc. IEEE Conference on Nanotechnology, Genoa, Italy, 2009.

    Google Scholar 

  54. P. Joshi, M. Leuchtenburg, P. Narayanan, and C. A. Moritz, Variation mitigation versus defect tolerance at the nanoscale, in Proc. Nanoelectronic Devices for Defense & Security Conference, Fort Lauderdale, FL, 2009.

    Google Scholar 

  55. Z. Chen et al., An integrated logic circuit assembled on a single carbon nanotube, Science, vol. 311, p. 1735, 2006.

    Article  Google Scholar 

  56. P. Narayanan, K. W. Park, C. O. Chui, and C. A. Moritz, Manufacturing pathway and associated challenges for nanoscale computational systems, in Proc. IEEE Conference on Nanotechnology, Genoa, Italy, 2009.

    Google Scholar 

  57. R. He, D. Gao, R. Fan, A. I. Hochbaum, C. Carraro, R. Maboudian, and P. Yang, Si nanowire bridges in microtrenches: integration of growth into device fabrication, Adv. Mater., vol. 17, pp. 2098–2102, 2005.

    Article  Google Scholar 

  58. Y. Shan and S. J. Fonash, Self-assembling silicon nanowires for device applications using the nanochannel-guided ‘grow-in-Place’ approach, ACS Nano, vol. 2, pp. 429–434, 2008.

    Article  Google Scholar 

  59. A. Ural, Y. Li, and H. Dai, Electric-field-aligned growth of single-walled carbon nanotubes on surfaces, Appl. Phys. Lett., vol. 81, pp. 3464–3466, 2002.

    Article  Google Scholar 

  60. O. Englander, D. Christensen, J. Kim, L. Lin, and S. J. S. Morris, Electric-field assisted growth and self-assembly of intrinsic silicon nanowires, Nano Lett., vol. 5, pp. 705–708, 2005.

    Article  Google Scholar 

  61. Y-T. Liu, X-M. Xie, Y-F. Gao, Q-P. Feng, L-R. Guo, X-H. Wang, and X-Y. Ye, Gas flow directed assembly of carbon nanotubes into horizontal arrays, Mater. Lett., vol. 61, pp. 334–338, 2007.

    Article  Google Scholar 

  62. X. Chen, M. Hirtz, H. Fuchs, and L. Chi, Fabrication of gradient mesostructures by Langmuir–Blodgett rotating transfer, Langmuir, vol. 23, pp. 2280–2283, 2007.

    Article  Google Scholar 

  63. D. Whang, S. Jin, and C. M. Lieber, Nanolithography using hierarchically assembled nanowire masks, Nano Lett., vol. 3, pp. 951–954, 2003.

    Article  Google Scholar 

  64. X. Xiong, L. Jaberansari, M. G. Hahm, A. Busnaina, and Y. J. Jung, Building highly organized single-walled carbon-nanotube networks using template-guided fluidic assembly, Small, vol. 3, pp. 2006–2010, 2007.

    Article  Google Scholar 

  65. K. Heo, E. Cho, J-E. Yang, M-H. Kim, M. Lee, B. Y. Lee, S. G. Kwon, M-S. Lee, M-H. Jo, H-J. Choi, T. Hyeon, and S. Hong, Large-scale assembly of silicon nanowire network-based devices using conventional microfabrication facilities, Nano Lett., vol. 8, pp. 4523–4527, 2008.

    Article  Google Scholar 

  66. B. J. Jordan, Y. Ofir, D. Patra, S. T. Caldwell, A. Kennedy, S. Joubanian, G. Rabani, G. Cooke, and V. M. Rotello, Controlled self-assembly of organic nanowires and platelets using dipolar and hydrogen-bonding interactions, Small, vol. 4, pp. 2074–2078, 2008.

    Article  Google Scholar 

  67. A. Javey, S. Nam, R. S. Friedman, H. Yan, and C. M. Lieber, Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics, Nano Lett., vol. 7, pp. 773–777, 2007.

    Article  Google Scholar 

  68. T. Martensson, P. Carlberg, M. Borgstrom, L. Montelius, W. Seifert, and L. Samuelson, Nanowire arrays defined by nanoimprint lithography, Nano Lett., vol. 4, pp. 699–702, 2004.

    Article  Google Scholar 

  69. S. J. Kang, C. Kocabas, H-S. Kim, Q. Cao, M. A. Meitl, D-Y. Khang, and J. A. Rogers, Printed multilayer superstructures of aligned single-walled carbon nanotubes for electronic applications, Nano Lett., vol. 7, pp. 3343–3348, 2007.

    Article  Google Scholar 

  70. M. C. McAlpine, H. Ahmad, D. Wang, and J. R. Heath, Highly ordered nanowire arrays on plastic substrates for ultrasensitive flexible chemical sensors, Nat. Mater., vol.6, pp. 379–384, 2007.

    Article  Google Scholar 

Download references

Acknowledgments

The authors acknowledge support from the Focus Center Research Program (FCRP) – Center on Functional Engineered Nano Architectonics (FENA). This work was also supported by the Center for Hierarchical Manufacturing (CHM/NSEC 0531171) University of Massachusetts at Amherst and NSF awards 0508382, 0541066 and 0915612.

There are several researchers who are actively contributing to various aspects of NASICs, in addition to the authors. Prof. Anderson at UMass is developing information-theoretical models for projecting the ultimate capabilities of NASICs. In addition to the efforts based on the promising ex situ techniques presented, experimental techniques are being investigated for in situ self-assembly-based NASIC fabric formation by Profs. Mihri and Cengiz Ozkan at UCR, as well as investigators in the UMass CHM Nanotechnology Center.

Profs. Pottier, Dezan, and Lagadec and their groups at Universite Occidentale in Bretagne, France, collaborate in developing CAD tools. Profs. Koren and Krishna at Umass are collaborating in devising techniques that allow efficient fault masking in NASICs.

The authors appreciate the valuable feedback and support at various phases of the project from Dr. Avouris, IBM; Dr. Kos Galatsis, UCLA; Profs. Kostya Likharev, Stony Brook University; Mark Tuominen, UMass; James Watkins, UMass; Richard Kiehl, UC Davis; Kang Wang, UCLA; and many others.

This project would have not been possible without the effort of current and former graduate students. Key contributors include Dr. Teng Wang, currently at Qualcomm; Dr. Yao Guo, currently at Peking University; Dr. Mahmoud Bennaser, currently at Kuwait University; Dr. Kyeon–Sik Shin, currently a post-doc at UCLA; Michael Leuchtenburg, Prachi Joshi, Lin Zhang, Jorge Kina, Pavan Panchakapeshan, Rahul Kulkarni, Mostafizur Rahman, Prasad Shabadi, Kyongwon Park, and Trong Tong Van.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA

    Csaba Andras Moritz

Authors
  1. Csaba Andras Moritz
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Pritish Narayanan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chi On Chui
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Csaba Andras Moritz .

Editor information

Editors and Affiliations

  1. Dept. Electrical Engineering, Princeton University, Olden Street, Princeton, 08544, New Jersey, USA

    Niraj K. Jha

  2. Dept. Electrical & Computer Engineering, University of Illinois, Urbana-Champaign, W. Main St. 1308, Urbana, 61801, Illinois, USA

    Deming Chen

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Moritz, C.A., Narayanan, P., Chui, C.O. (2011). Nanoscale Application-Specific Integrated Circuits. In: Jha, N., Chen, D. (eds) Nanoelectronic Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7609-3_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7609-3_7

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-7444-0

  • Online ISBN: 978-1-4419-7609-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation