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Nanoelectronic Circuit Design pp 153–187Cite as

Reliable Circuits Design with Nanowire Arrays

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Abstract

The emergence of different fabrication techniques of silicon nanowires (SiNWs) raises the question of finding a suitable architectural organization of circuits based on them. Despite the possibility of building conventional CMOS circuits with SiNWs, the ability to arrange them into regular arrays, called crossbars, offers the opportunity to achieve higher integration densities. In such arrays, molecular switches or phase-change materials are grafted at the crosspoints, i.e., the crossing nanowires, in order to perform computation or storage. Given the fact that the technology is not mature, a hybridization of CMOS circuits with nanowire arrays seems to be the most promising approach.

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Notes

  1. 1.

    The authors would like to acknowledge those who contributed to [1].

  2. 2.

    If we consider short-channel transistors, then the saturation current is proportional to (VA,i  − V th) and δ = (α + υ)/q.

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Author information

Authors and Affiliations

  1. Institute of Electrical Engineering, EPFL, Lausanne, Switzerland

    Giovanni De Micheli

Authors
  1. M. Haykel Ben Jamaa
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  2. Giovanni De Micheli
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Corresponding author

Correspondence to Giovanni De Micheli .

Editor information

Editors and Affiliations

  1. Dept. Electrical Engineering, Princeton University, Olden Street, Princeton, 08544, New Jersey, USA

    Niraj K. Jha

  2. Dept. Electrical & Computer Engineering, University of Illinois, Urbana-Champaign, W. Main St. 1308, Urbana, 61801, Illinois, USA

    Deming Chen

Appendices

Exercise 1 Delay in a Crossbar

Consider the following NxN crossbar circuit with N nanowires in every plane and M = log2(N) access transistors in the decoder of every plane. Determine the delay through the crossbar when the address corrsponding to the crosspoint (X,Y) is activated (X and Y are between 1 and M). Assume the following parameters:

  • Decoder parameters:

    • On-resistance of an access transistor: Ron = 10 kΩ

    • Off-resistance of an access transistor: Roff = 100 MΩ

    • Drain/source capacitances of an access transistor: CD/S = 1 fF

  • Parameters of the functional part of the crossbar

    • Resistance of a nanowire length unit equal to the nanowire pitch: RNW = 100 Ω

    • Capacitance of a molecular switch: CS = 2 fF

    • Resistance through a molecular switch: RS = 1 kΩ

    • Parasistic capacitance between crossing nanowires, parallel nanowires and between the nanowires and the substrate: not included

      Ex. Figure 1
      figure 18_5

      Baseline crossbar architecture

      Full size image

Exercise 2 Process Optimization

In goal of this exercise is to optimize the geometry of mask used in the MSPT process. The MSPT can used iteratively, starting with a given sacrificial layer, in order to define the spacers that may be used as sacrifical layers in the following steps.

This techniques envolves the deposition of a first sacrificial layer (1st step) with the width W and pitch P. Then, a sacrificial layer with the height W1 = qW is deposited (2nd step) and etched (3rd step) in order the form the sacrifical layer with the width W1 and a smaller pitch than P (4th step). These steps can be repeated with a following deposition of a layer with a height W2 = q W1 (step 5 to 7) in order to decrease the pitch further.

Questions taken from [50]:

  1. 1

    Calculate the extension of the spacer underneath and beyond the first sacrificial layer after n iterations (lout(n) and lin(n) respectively).

  2. 2

    For a large number of iterations, calculate the optimal values for q and W/P.

    Ex. Figure 2
    figure 19_5

    Multiplicative road of the multi-spacer technique [50]

    Full size image

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Jamaa, M.H.B., De Micheli, G. (2011). Reliable Circuits Design with Nanowire Arrays. In: Jha, N., Chen, D. (eds) Nanoelectronic Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7609-3_5

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