FinFET SRAM Design



We present a comprehensive review of finFET devices taking into consideration different levels of interest ranging from the physics of FinFET devices, design considertaions, and applications to memory design and statistics.

We start with fundamental equations that describe the advantages of finFETs in terms of leakage reduction and ON current improvement compared to planar devices. Following this, we look at variability aspects of finFETs such as quantization (L, W, Vt) from a memory design perspective. We then lay the foundation for SRAM yield optimization in terms of cell dynamic behaviour and study different cell designs that leverage the finFET device structure. We also apply statistical methodology to evaluate the finFET variability.


FinFET SRAM Statistical Leakage double gate backgate MOSFET 


  1. 1.
    E.J. Nowak, I. Aller, T. Ludwig, K. Kim, R.V. Joshi, C.T. Chuang, K. Bernstein, and R. Puri, “Turning silicon on its edge,” IEEE Circ Dev Mag 20(1): 20–31, Jan./Feb. 2004.CrossRefGoogle Scholar
  2. 2.
    K. Kim and J.G. Fossum, “Double-gate CMOS: Symmetrical versus asymmetrical-gate devices,” IEEE Trans Electron Dev 48: 294–299, Feb. 2001.CrossRefGoogle Scholar
  3. 3.
    Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge, UK: Cambridge University Press, 1998.Google Scholar
  4. 4.
    D. Vasileska and Z. Ren, “SCHRED-2.0 Manual,” Arizona State University, Tempe, AZ, and Purdue University, West Lafayette, IN, Feb. 2000.Google Scholar
  5. 5.
    K. Kim, K. Das, R.V. Joshi, and C.-T. Chuang, “Leakage power analysis of 25-nm double-gate CMOS devices and circuits,” IEEE Trans Electron Dev 52(5): 980–986, May 2005.CrossRefGoogle Scholar
  6. 6.
    D.J. Frank, S.E. Laux, and M.V. Fischetti, “Monte Carlo simulation of a 30-nm dual-gate MOSFET: How short can Si go?,” in Proc. Int. Electron Devices Meeting, pp. 553–556, 1992.Google Scholar
  7. 7.
    H.-S.P. Wong et al., “Nanoscale CMOS,” in Proc. IEEE, pp. 537–570, Apr. 1999.Google Scholar
  8. 8.
    MEDICI: Two-dimensional device simulation, Mountain View, CA: Synopsys, Inc., 2003.
  9. 9.
    H.-K. Lim and J.G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans Electron Dev 18: 1244–1251, Oct. 1983.Google Scholar
  10. 10.
    M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Optimal design of triple-gate devices for high-performance and low-power applications,” IEEE Trans. Electron Dev 55(9): 2423–2428 Sep. 2008.CrossRefGoogle Scholar
  11. 11.
    R.V. Joshi, S. Mukhopadhyay, D.W. Plass, Y.H. Chan, C.-T. Chuang, and Y. Tan, “Design of sub-90 nm low-power and variation tolerant PD/SOI SRAM cell based on dynamic stability metrics,” IEEE J Solid-State Circuits 44: 965–976, Mar. 2009.CrossRefGoogle Scholar
  12. 12.
    Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and B. Nikolic, “FinFET-based SRAM design,” in Proc. Int. Symp. Lower Power Elec. Des., pp. 2–7, Aug. 2005.Google Scholar
  13. 13.
    R.V. Joshi, R.Q. Williams, E. Nowak, K. Kim, J. Beintner, T. Ludwig, I. Aller, and C. Chuang, “FinFET SRAM for high-performance and low-power applications,” in Proc. European Solid-State Device Research Conference, pp. 69–72, Sep. 2004.Google Scholar
  14. 14.
    C.-T. Chuang, K. Bernstein, R.V. Joshi, R. Puri, K. Kim, E.J. Nowak, T. Ludwig, and I. Aller, “Scaling planar silicon devices,” IEEE Circuits Dev Mag 20(1): 6–19, Jan./Feb. 2004 (invited).CrossRefGoogle Scholar
  15. 15.
    Y. Liu, M. Masahara, K. Ishii, T. Sekigawa, H. Takashima, H. Yamauchi, and E. Suzuki, “A high-threshold voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel,” IEEE Electron Dev Lett 25(7): 510–512, Jul. 2004.CrossRefGoogle Scholar
  16. 16.
    R.A. Thakker, C. Sathe, A.B. Sachid, M.S. Baghini, V.R. Rao, and M.B. Patil, “A table-based approach to study the impact of process variations on FinFET circuit performance,” IEEE Trans CAD 29(4): 627–631, July 2010.Google Scholar
  17. 17.
    R.V. Joshi, J.A. Pascual-Gutiérrez, and C.T. Chuang, “3-D thermal modeling of FinFET,” in Proc. European Solid-State Device Research Conference, pp. 77–80, 2005.Google Scholar
  18. 18.
    J.A. Pascual-Gutiérrez, J.Y. Murthy, R. Viskanta, R.V. Joshi, and C. Chuang, “Simulation of nano-scale multi-fingered PD/SOI MOSFETs using Boltzmann transport equation,” in ASME Heat Transfer/Fluids Engineering Summer Conference, July 2004.Google Scholar
  19. 19.
    BSIMPD MOSFET Model User’s Manual:
  20. 20.
    R.V. Joshi, K. Kim, R.Q. Williams, E.J. Nowak, and C.-T. Chuang, “A high-performance, low-leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology,” in Proc. Int. Conf. on VLSI Design, pp. 665–672, Jan. 2007.Google Scholar
  21. 21.
    K. Kim, C.-T. Chuang, J.B. Kuang, H.C. Ngo, and K. Nowka, “Low-power high-performance asymmetrical double-gate circuits using back-gate-controlled wide-tunable-range diode voltage,” IEEE Trans Electron Dev 54(9): 2263–2368, Sep. 2007.CrossRefGoogle Scholar
  22. 22.
    K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70 Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply,” in Proc. IEEE Int. Solid-State Circuits Conference, pp. 474–475, Feb. 2005.Google Scholar
  23. 23.
    J.G. Fossum, K. Kim, and Y. Chong, “Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current,” IEEE Trans Electron Dev 46: 2195–2200, Nov. 1999.CrossRefGoogle Scholar
  24. 24.
    M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura, and T. Kawahara, “Low-power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology,” in Proc. Symp. VLSI Circuits, pp. 288–291, Jun. 2004.Google Scholar
  25. 25.
    V. Ramadurai, R.V. Joshi, and R. Kanj, “A disturb decoupled column select 8T SRAM cell,” in Proc. Custom Integrated Circuits Conference, pp. 25–28, Sep. 2007.Google Scholar
  26. 26.
    M.H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, “High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices,” IEEE Trans Electron Dev 53: 2370–2377, Sep. 2006.CrossRefGoogle Scholar
  27. 27.
    R. Kanj, R.V. Joshi, K. Kim, R. Williams, and S. Nassif, “Statistical evaluation of split gate opportunities for improved 8T/6T column-decoupled SRAM cell yield,” in Proc. Int. Symp. Quality Electronic Design, pp. 702–707, Mar. 2008.Google Scholar
  28. 28.
    International Technology Roadmap for Semiconductors, 2004
  29. 29.
    J.A. López-Villanueva et al., “Effects of inversion-layer centroid on the performance of double-gate MOSFET’s,” IEEE Trans. Electron Devices, 47:141–146, Jan. 2000.Google Scholar
  30. 30.
    H. Ananthan, C.H. Kim, and K. Roy, “Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS” International Symposium on Low Power Electronics and Design, 8–13, 2004.Google Scholar
  31. 31.
    H. Ananthan and K. Roy, “Technology-circuit co-design in width-quantized quasi-planar double-gate SRAM”, International Conference on Integrated Circuit Design and Technology, pp. 155–160Google Scholar
  32. 32.
    L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab, A.W. Topol, C.D. Adams, K.W. Guarini, and W. Haensch, “Stable SRAM cell design for the 32 nm node and beyond”, 2005 Symposium on VLSI Technology, pp. 128–129Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.IBMThomas J. Watson Research CenterYorktown HeightsUSA

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