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Nanoelectronic Circuit Design pp 1–22Cite as

Introduction to Nanotechnology

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Abstract

The semiconductor industry has showcased a spectacular exponential growth in the number of transistors per integrated circuit for several decades, as predicted by Moore’s law. Figure 1 shows the future technology trend predicted by ITRS (International Technology Roadmap for Semiconductors) [1]. By 2023, the physical gate length would scale down to 4.5 nm. Actually, according to a study [2], future devices could theoretically scale down to 1.5 nm with 0.04 ps switching speed and 0.017 eV energy consumption. However, maintaining such an exponential growth rate is a major challenge. Physical dimensions and electrostatic limitations faced by conventional process and fabrication technologies will likely thwart the dimensional scaling of complementary metal-oxide-semiconductor (CMOS) devices within the next decade. Figure 2 from ITRS shows that after 2016, the manufacturable solutions are unknown (the shaded area).

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA

    Deming Chen

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  1. Deming Chen
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  2. Niraj K. Jha
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Correspondence to Deming Chen .

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Editors and Affiliations

  1. Dept. Electrical Engineering, Princeton University, Olden Street, Princeton, 08544, New Jersey, USA

    Niraj K. Jha

  2. Dept. Electrical & Computer Engineering, University of Illinois, Urbana-Champaign, W. Main St. 1308, Urbana, 61801, Illinois, USA

    Deming Chen

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Chen, D., Jha, N.K. (2011). Introduction to Nanotechnology. In: Jha, N., Chen, D. (eds) Nanoelectronic Circuit Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7609-3_1

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  • DOI: https://doi.org/10.1007/978-1-4419-7609-3_1

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