Putting Mitigation Techniques at Work

  • Niccolò BattezzatiEmail author
  • Luca Sterpone
  • Massimo Violante


The developed place and route algorithms have been experimentally evaluated in order to probe the efficiency and the improvements of performances with respect to standard TMR circuits implemented on SRAM-based FPGAs. The place and route-hardened circuits have been compared with the ones generated by the Xilinx ISE tool chain version 9.2.


Logic Gate Fault Injection Device Under Test Mitigation Technique Benchmark Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Niccolò Battezzati
    • 1
    Email author
  • Luca Sterpone
    • 2
  • Massimo Violante
    • 1
  1. 1.Dipto. Automatica e InformaticaPolitecnico di TorinoTorinoItaly
  2. 2.Politecnico di TorinoTorinoItaly

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