Putting Mitigation Techniques at Work
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The developed place and route algorithms have been experimentally evaluated in order to probe the efficiency and the improvements of performances with respect to standard TMR circuits implemented on SRAM-based FPGAs. The place and route-hardened circuits have been compared with the ones generated by the Xilinx ISE tool chain version 9.2.
KeywordsLogic Gate Fault Injection Device Under Test Mitigation Technique Benchmark Circuit
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