Reconfigurable Field Programmable Gate Arrays: Hardening Solutions

  • Niccolò BattezzatiEmail author
  • Luca Sterpone
  • Massimo Violante


During the past years, several mitigation techniques have been proposed in order to increase the reliability of circuits of avionics and space applications and, in particular, to remove single and multiple points of failure from the designs. Depending on the kind of FPGA technology, several mitigation techniques have been proposed. These techniques rely, on the one hand, on technological modifications, in part sustained from the progressive improvement of the technology realization process and in part from necessity of increasing the reliability and the capacity of FPGA devices to tolerate faults; on the other hand, mitigation techniques can be applied at the application level, to exploit commercial technology anyhow achieving the required reliability degree.


Field Programmable Gate Array Very Large Scale Integration Soft Error Register Transfer Level Single Event Transient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    The art of error correcting codes, Robert H. Morelas-Zaragoza, Wiley, 1996.Google Scholar
  2. 2.
    High level synthesis with synphony c compiler.Google Scholar
  3. 3.
    Actel Corporation, Using synplify to design in actel radiation-hardened fpgas, application note ac139 ed., May 2000.Google Scholar
  4. 4.
    S.N. Adya and I.L. Markov, Fixed-outline floorplanning: Enabling hierarchical design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (2003), no. 6, 1120–1135.CrossRefGoogle Scholar
  5. 5.
    M. Alderighi, F. Casini, S. D’Angelo, M. Mancini, A. Marmo, S. Pastore, and G.R. Sechi, A tool for injecting seu-like faults into the configuration control mechanism of xilinx virtex fpgas, Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, 2003, pp. 71–78.Google Scholar
  6. 6.
    M.J. Alexander and G. Robins, New performance-driven fpga routing algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15 (1996), no. 12, 1505–1517.CrossRefGoogle Scholar
  7. 7.
    J.L. Andrews, J.E. Schroeder, B.L. Gingerich, W.A. Kolasinski, R. Koga, and S.E. Diehl, Single event error immune cmos ram, IEEE Transactions on Nuclear Science 29 (1982), no. 6, 2040–2043.CrossRefGoogle Scholar
  8. 8.
    Y. Arima, T. Yamashita, Y. Komatsu, T. Fujimoto, and K. Ishibashi, Cosmic-ray immune latch circuit for 90 nm technology and beyond, Digest of Technical Papers of the IEEE International Solid-State Circuits Conference San Francisco, CA, vol. 1, 2004, pp. 492–493.Google Scholar
  9. 9.
    A.J. Auberton-Herve, Soi: Materials to systems, Electron Devices Meeting, 1996. IEDM ’96., International, San Francisco, CA, 8–11 1996, pp. 3–10.Google Scholar
  10. 10.J.R.
    Azambuja, F. Sousa, L. Rosa, and F.L. Kastensmidt, Evaluating large grain tmr and selective partial reconfiguration for soft error mitigation in sram-based fpgas, Proceedings of the 15th IEEE International On-Line Testing Symposium, Lisbon 2009.Google Scholar
  11. 11.
    M. Bagatin, G. Cellere, S. Gerardin, A. Paccagnella, A. Visconti, S. Beltrami, and M. Maccarrone, Single event effects in 1gbit 90 nm nand flash memories under operating conditions, On-Line Testing Symposium, 2007. IOLTS 07. Proceedings of the 13th IEEE International, Lisbon, 8–11 2007, pp. 146–151.Google Scholar
  12. 12.
    R.J. Baker, Cmos: Circuit design, layout, and simulation, vol. 1, Wiley-IEEE, Piscataway, NJ, 2007.Google Scholar
  13. 13.
    A. Balasubramanian, B.L. Bhuva, J.D. Black, and L.W. Massengill, Rhbd techniques for mitigating effects of single-event hits using guard-gates, IEEE Transactions on Nuclear Science 52 (2005), no. 6, 2531–2535.CrossRefGoogle Scholar
  14. 14.
    H.J. Barnaby, Total-ionizing-dose effects in modern cmos technologies, IEEE Transactions on Nuclear Science 53 (2006), no. 6, 3103–3121.CrossRefGoogle Scholar
  15. 15.
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, and M. Violante, Methodologies to study frequency-dependent single event effects sensitivity in flash-based fpgas, IEEE Transactions on Nuclear Science 56 (2009), no. 6, 3534–3541.CrossRefGoogle Scholar
  16. 16.
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, and M. Violante, On the evaluation of radiation-induced transient faults in flash-based fpgas, On-Line Testing Symposium, 2008. IOLTS ’08. Proceedings of the 14th IEEE International, Washington, DC, 7–9 2008, pp. 135–140.Google Scholar
  17. 17.
    N. Battezzati, D. Serrone, and M. Violante, A new framework for the automatic insertion of mitigation structures in circuits netlists. Proceedings of the 16th IEEE International On-Line Testing Symposium, Corfu Island, 2010.Google Scholar
  18. 18.
    M.P. Baze, S.P. Buchner, and D. McMorrow, A digital cmos design technique for seu hardening, IEEE Transactions on Nuclear Science 47 (2000), no. 6, 2603–2608.CrossRefGoogle Scholar
  19. 19.
    P. Bellows and B. Hutchings, Jhdl – an hdl for reconfigurable systems, Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, Napavalley, CA, 1998.Google Scholar
  20. 20.
    J.M. Benedetto, P.H. Eaton, D.G. Mavis, M. Gadlage, and T. Turflinger, Digital single event transient trends with technology node scaling, IEEE Transactions on Nuclear Science 53 (2006), no. 6, 3462–3465.CrossRefGoogle Scholar
  21. 21.
    E. Bergeron, M. Feeley, and J.P. David, Toward on-chip jit synthesis on xilinx virtexii-pro fpgas, IEEE Northeast Workshop on Circuits and Systems, Montreal, 2007, pp. 642–645.Google Scholar
  22. 22.
    V. Betz and J. Rose, Directional bias and non-uniformity in fpga global routing architectures, Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers, proceedings of the 1996 IEEE/ACM International Conference on San Jose, CA, 10–14 1996, pp. 652–659.Google Scholar
  23. 23.
    H.E. Boesch, Jr., T.L. Taylor, L.R. Hite, and W.E. Bailey, Time-dependent hole and electron trapping effects in simox buried oxides, IEEE Transactions on Nuclear Science 37 (1990), no. 6, 1982–1989.CrossRefGoogle Scholar
  24. 24.
    B. Bridgford, C. Carmichael, and C.W. Tseng, Correcting single-event upsets in virtex-ii platform fpga configuration memory, Xilinx, xapp779 ed., February 2007.Google Scholar
  25. 25.
    P. Brinkley, A. Carmichael, and C. Carmichael, Seu mitigation design techniques for xqr4000xl, Xilinx, xapp181 ed., 2000.Google Scholar
  26. 26.
    M. Bruel, Silicon on insulator material technology, Electronics Letters 31 (1995), no. 14, 1201–1202.CrossRefGoogle Scholar
  27. 27.
    BYU Configurable Computing Group, Byu-lanl triple modular redundancy, usage guide, version 0.5.2 ed., 2009.Google Scholar
  28. 28.
    T. Calin, M. Nicolaidis, and R. Velazco, Upset hardened memory design for submicron cmos technology, IEEE Transactions on Nuclear Science 43 (1996), no. 1, 2874–2878.CrossRefGoogle Scholar
  29. 29.
    A.B. Campbell, W.J. Stapor, R. Koga, and W.A. Kolasinski, Correlated proton and heavy ion upset measurements on idt static rams, IEEE Transactions on Nuclear Science 32 (1985), no. 6, 4150–4154.CrossRefGoogle Scholar
  30. 30.
    C. Carmichael, Triple module redundancy design techniques for virtex fpgas, Xilinx, xapp197 (v1.0) ed., 2001.Google Scholar
  31. 31.
    C. Carmichael, M. Caffrey, and A. Salazar, Correcting single event upset through virtex partial reconfiguration, Xilinx, xapp216 ed., 2000.Google Scholar
  32. 32.
    V.F. Cavrois, V. Pouget, D. McMorrow, J.R. Schwank, N. Fel, F. Essely, R.S. Flores, P. Paillet, M. Gaillardin, D. Kobayashi, J.S. Melinger, O. Duhamel, P.E. Dodd, and M.R. Shaneyfelt, Investigation of the propagation induced pulse broadening (pipb) effect on single event transients in soi and bulk inverter chains, IEEE Transactions on Nuclear Science 55 (2008), no. 6, 2842–2853.CrossRefGoogle Scholar
  33. 33.
    M. Ceschia, M. Bellato, A. Paccagnella, and A. Kaminski, Ion beam testing of altera apex fpgas, Radiation Effects Data Workshop, 2002 IEEE, Phoenix, AZ, 2002, pp. 45–50.Google Scholar
  34. 34.
    B. Chappell, S.E. Schuster, and G.A. Sai-Halasz, Stability and ser analysis of static ram cells, IEEE Transactions on Electronic Devices 32 (1985), no. 2, 463–470.CrossRefGoogle Scholar
  35. 35.
    S. Chiang, R. Forouhi, W. Chen, F. Hawley, D. McCollum, E. Hamdy, and C. Hu, Antifuse structure comparison for field programmable gate arrays, International Electron Devices Meeting Technical Digest, San Fransisco, CA, 1992, pp. 611–614.Google Scholar
  36. 36.
    L.T. Clark, K.C. Mohr, and K.E. Holbert, Reverse-body biasing for radiation-hard by design logic gates, Proceedings of the 45th annual IEEE international Reliability physics symposium, Phoenix, AZ, 2007.Google Scholar
  37. 37.
    L.T. Clark, K.E. Nielsen, and K.E. Holbert, Radiation hardened by design digital i/o for high see and tid immunity, IEEE Transactions on Nuclear Science 56 (2009), no. 6, 3408–3414.CrossRefGoogle Scholar
  38. 38.
    S. Corbetta, M. Morandi, M. Novati, M.D. Santambrogio, D. Sciuto, and P. Spoletini, Internal and external bitstream relocation for partial dynamic reconfiguration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (2009), no. 11, 1650–1654.CrossRefGoogle Scholar
  39. 39.
    J.D. Crawford, Edif: A mechanism for the exchange of design information, IEEE Design and Test of Computers 2 (1985), no. 1, 63–69.CrossRefGoogle Scholar
  40. 40.
    F.G. de Lima Kastensmidt, G. Neuberger, R.F. Hentschke, L. Carro, and R. Reis, Designing fault-tolerant techniques for sram-based fpgas, IEEE Design and Test of Computers 21 (2004), no. 6, 552–562.CrossRefGoogle Scholar
  41. 41.
    R.F. DeKeersmaecker and D.J. DiMaria, Electron trapping and detrapping characteristics of arsenic-implanted sio[sub 2] layers, Journal of Applied Physics 51 (1980), no. 2, 1085–1101.CrossRefGoogle Scholar
  42. 42.
    R.A.B. Devine, W.L. Warren, J.B. Xu, I.H. Wilson, P. Paillet, and J.L. Leray, Oxygen gettering and oxide degradation during annealing of si/sio2/si structures, Journal of Applied Physics 77 (1995), no. 1, 175–186.CrossRefGoogle Scholar
  43. 43.
    Y.S. Dhillon, A.U. Diril, and A. Chatterjee, Soft-error tolerance analysis and optimization of nanometer circuits, Design, Automation and Test in Europe, 2005. Proceedings, Washington, DC, vol. 1, 7–11 2005, pp. 288–293.Google Scholar
  44. 44.
    Y.S. Dhillon, A.U. Diril, A. Chatterjee, and C. Metra, Load and logic co-optimization for design of soft-error resistant nanometer cmos circuits, On-Line Testing Symposium, 2005. IOLTS 2005. Proceedings of the 11th IEEE International, French Riviera, 6–8 2005, pp. 35–40.Google Scholar
  45. 45.
    C. Ebeling, L. McMurchie, S.A. Hauck, and S. Burns, Placement and routing tools for the triptych fpga, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (1995), no. 4, 473–482.CrossRefGoogle Scholar
  46. 46.
    L.J. Edgar, Method and apparatus for controlling electric currents, Tech. Report 1745175, January 1930.Google Scholar
  47. 47.
    L.J. Edgar, Device for controlling electric current, Tech. Report 1900018, March 1933.Google Scholar
  48. 48.
    E. Eto, Difference-based partial reconfiguration, Xilinx, xapp290 (v2.0) ed., December 2007.Google Scholar
  49. 49.
    J.P. Eurich and G. Roth, Edif grows up, IEEE Spectrum 27 (1990), no. 11.Google Scholar
  50. 50.
    V. Ferlet-Cavrois, P. Paillet, D. McMorrow, N. Fel, J. Baggio, S. Girard, O. Duhamel, J.S. Melinger, M. Gaillardin, J.R. Schwank, P.E. Dodd, M.R. Shaneyfelt, and J.A. Felix, New insights into single event transient propagation in chains of inverters – evidence for propagation-induced pulse broadening, IEEE Transactions on Nuclear Science 54 (2007), no. 6, 2338–2346.CrossRefGoogle Scholar
  51. 51.
    E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, and A. Salazar, Radiation test results of the virtex fpga and zbt sram for space based reconfigurable computing, Military and Aerospace Programmable Logic Devices (MAPLD) Conference, Washington, C, 1999.Google Scholar
  52. 52.
    T. Grötker, S. Liao, G. Martin, and S. Swan, System design with systemc, Springer, London, UK, 2002.Google Scholar
  53. 53.
    S. Habinc, Functional triple modular redundancy (ftmr) vhdl design methodology for redundancy in combinational and sequential logic, Gaisler Research, 2002.Google Scholar
  54. 54.
    J. Hagemeyer, B. Keltelhoit, M. Koester, and M. Porrmann, A design methodology for communication infrastructures on partially reconfigurable fpgas, International Conference on Field Programmable Logic and Applications, Amsterdam, 2007, pp. 331–338.Google Scholar
  55. 55.
    E. Hamdy, J. McCollum, S.-O. Chen, S. Chiang, S. Eltoukhy, J. Chang, T. Speers, and A. Mohsen, Dielectric based antifuse for logic and memory ics, International Electron Devices Meeting Technical Digest, San Francisco, CA, 1988, pp. 786–789.Google Scholar
  56. 56.
    K. Hass, J. Gambles, B. Walker, and M. Zampaglione, Mitigating single event upsets from combinational logic, Proceedings of the 7th Annual NASA Symposium on VLSI Design, Piscataway, USA, 1998.Google Scholar
  57. 57.
    V. Joshi, R.R. Rao, D. Blaauw, and D. Sylvester, Logic ser reduction through flip flop redesign, Quality Electronic Design, 2006. ISQED ’06. Proceedings of the 7th International Symposium on, Washington, DC, 27–29 2006, pp. 611–616.Google Scholar
  58. 58.
    H.J. Kahn and R.F. Goldman, The electronic design interchange format edif: present and future, Proceedings of the 29th ACM/IEEE Design Automation Conference, Anaheim, CA, 1992.Google Scholar
  59. 59.
    T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla, and S. Borkar, Selective node engineering for chip-level soft error rate improvement [in cmos], VLSI Circuits Digest of Technical Papers, 2002. Symposium on, Piscataway, USA, 2002, pp. 204–205.Google Scholar
  60. 60.
    M. Karunaratne, A. Sagahayroon, and S. Prodhuturi, Rtl fault modeling. Proceedings of the 48th Midwest Symposium on Circuits and Systems, Cincinnati, OH, 2005.Google Scholar
  61. 61.
    F.L. Kastensmidt, L. Sterpone, L. Carro, and M.S. Reorda, On the optimal design of triple modular redundancy logic for sram-based fpgas, Design, Automation and Test in Europe, 2005. Proceedings, Munich, vol. 2, 7–11 2005, pp. 1290–1295Google Scholar
  62. 62.
    P.J. Kim, D.S. Ku, L.S. Jeong, J.H. Yun, S.Y. Choi, and J.B. Kim, Electrical properties of pip anti-fuse for the logic circuit configuration, Proceedings of the SICE 2003 Annual Conference, vol. 3, Piscataway, USA, 2003, pp. 2980–2983.Google Scholar
  63. 63.
    R. Koga, J. George, G. Swift, C. Yui, L. Edmonds, C. Carmichael, T. Langley, P. Murray, K. Lanes, and M. Napier, Comparison of xilinx virtex-ii fpga see sensitivities to protons and heavy ions, IEEE Transactions on Nuclear Science 51 (2004), no. 5, 2825–2833.CrossRefGoogle Scholar
  64. 64.
    G.M. Koob and C. Lau, Foundations of dependable computing: Models and frameworks for dependable systems, Springer, New York, NY 1994.zbMATHGoogle Scholar
  65. 65.
    M. Köster, W. Luk, J. Hagemeyer, and M. Porrmann, Design optimizations to improve placeability of partial reconfiguration modules, Proceedings of DATE: Design, Automation and Test in Europe, Nice, 2009.Google Scholar
  66. 66.
    M. Köster, W. Luk, J. Hagemeyer, M. Porrmann, and U. Rueckert, Design optimizations for tiled partially reconfigurable systems, IEEE Transactions on Very Large Scale Integration Systems (2010).Google Scholar
  67. 67.
    A.A. Kountouris and C. Wolinski, A method for the generation of hdl code at the rtl level from a high-level formal specification language, Proceedings of the 40th Midwest Symposium on Circuits and Systems, Piscataway, USA, 1997.Google Scholar
  68. 68.
    Y.E. Krasteva, E. de la Torre, T. Riesgo, and D. Joly, Virtex ii fpga bitstream manipulation: Application to reconfiguration control systems, International Conference on Field Programmable Logic and Applications Madrid, 2006, pp. 1–4.Google Scholar
  69. 69.
    R.C. Lacoe, J.V. Osborn, R. Koga, S. Brown, and D.C. Mayer, Application of hardness-by-design methodology to radiation-tolerant asic technologies, IEEE Transactions on Nuclear Science 47 (2000), no. 6, 2334–2341.CrossRefGoogle Scholar
  70. 70.
    R.C. Lacoe, J.V. Osborn, D.C. Mayer, S. Brown, and J. Gambles, Total-dose tolerance of the commercial Taiwan semiconductor manufacturing company (tsmc) 0.35- mu;m cmos process, Radiation Effects Data Workshop IEEE, Vancouver, BC 2001, pp. 72–76.Google Scholar
  71. 71.
    C.Y. Lee, An algorithm for path connections and its applications, IEEE Transactions on Electronic Computers EC-10 (1961), no. 3, 346–365.CrossRefGoogle Scholar
  72. 72.
    W. Lei, C. Lei, W. Zhiping, S. Huabo, and W. Shuo, A novel high-density single-event upset hardened configurable sram applied to fpga, Proceedings of the International Conference on Reconfigurable Computing and FPGAs, QuintanaRoo 2009, pp. 1–5.Google Scholar
  73. 73.
    W. Liang, Y. Suge, Z. Yuanfu, and F. Long, An seu-tolerant programmable frequency divider, Proceedings of the 8th International Symposium on Quality Electronic Design, San Jose, CA, 2007, pp. 899–904.Google Scholar
  74. 74.
    H.-K. Lim and J.G. Fossum, Threshold voltage of thin-film silicon-on-insulator (soi) mosfet’s, IEEE Transactions on Electron Devices 30 (1983), no. 10, 1244–1251.CrossRefGoogle Scholar
  75. 75.
    F. Lima, L. Carro, and R. Reis, Designing fault tolerant systems into sram-based fpgas, Design Automation Conference, 2003. Proceedings, Anaheim, CA, 2–6 2003, pp. 650–655.Google Scholar
  76. 76.
    S. Lin and D.J. Costello Jr., Error control coding: Fundamentals and applications, 2 ed., Prentice Hall, Englewood Cliffs, NJ, 2004.Google Scholar
  77. 77.
    R. Lipsett, C.F. Schaefer, and C. Ussery, Vhdl, hardware description and design, Springer, Piscataway, USA, 1989.Google Scholar
  78. 78.
    F. Miller, N. Buard, G. Hubert, S. Alestra, G. Baudrillard, T. Carriere, R. Gaillard, J.M. Palau, F. Saigne, and P. Fouillat, Laser mapping of sram sensitive cells. a way to obtain input parameters for DASIE calculation code, Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. Proceedings of the 8th European Conference on, Cap d’Agde 19-23 2005, pp. E2–1–E2–7.Google Scholar
  79. 79.
    K. Ming-Dou, J. Hsin-Chin, P. Jeng-Jie, and S. Tzay-Luen, Automatic methodology for placing the guard rings into chip layout to prevent latchup in cmos ic’s, Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, 2001, pp.113–116.Google Scholar
  80. 80.
    K. Ming-Dou and L. Wen-Yu, Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk cmos technology, IEEE Transactions on Semiconductor Manufacturing 16 (Piscataway, USA, 2003), no. 2, 319–334.CrossRefGoogle Scholar
  81. 81.
    S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K.S. Kim, Robust system design with built-in soft-error resilience, Computer 38 (2005), no. 2, 43–52.CrossRefGoogle Scholar
  82. 82.
    P. Mongkolkachit and B. Bhuva, Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic, IEEE Transactions on Device and Materials Reliability 3 (2003), no. 3, 89–92.CrossRefGoogle Scholar
  83. 83.
    T. Monnier, F.M. Roche, and G. Cathebras, Flip-flop hardening for space applications, Proceedings of the International Workshop on Memory Technology, Design and Testing, San Jose, CA, 1998, pp. 104–107.Google Scholar
  84. 84.
    D.P. Montminy, R.O. Baldwin, P.D. Williams, and B.E. Mullins, Using relocatable bitstreams for fault tolerance, Second NASA/ESA Conference on Adaptive Hardware and Systems, Edinburgh, 2007, pp. 701–708.Google Scholar
  85. 85.
    A. Montone, F. Redaelli, M.D. Santambrogio, and S.O. Memik, A reconfiguration-aware floorplacer for fpgas, Reconfigurable Computing and FPGAs, 2008. ReConFig ’08. International Conference on, Cancur 3–5 2008, pp. 109–114.Google Scholar
  86. 86.
    W. Morris, Latchup in cmos, Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International, 30 2003, pp. 76–84.Google Scholar
  87. 87.
    B.J. Mrstik, H.L. Hughes, P.J. McMarr, R.K. Lawrence, D.I. Ma, I.P. Isaacson, and R.A. Walker, Hole and electron trapping in ion implanted thermal oxides and simox, IEEE Transactions on Nuclear Science 47 (Piscataway, USA, 2000), no. 6, 2189–2195.CrossRefGoogle Scholar
  88. 88.
    T. Murooka, A. Takahara, T. Miyazaki, and A. Tsutsui, An architecture-oriented routing method for fpgas having rich hierarchical routing resources, Asia and South Pacific Design Automation Conference 1998. Proceedings of the ASP-DAC ’98, Yokohama, 1998, pp. 527–533.Google Scholar
  89. 89.
    S.R. Nariani, C.T. Gabriel, and V. Jain, Improved reliability of amorphous silicon anti-fuse used in high speed fpga, Proceedings of the IEEE Custom Integrated Circuits Conference, 1994, pp. 484–487.Google Scholar
  90. 90.
    R. Naseer, J. Draper, Y. Boulghassoul, S. DasGupta, and A. Witulski, Critical charge and set pulse widths for combinational logic in commercial 90 nm cmos technology, GLSVLSI ’07: Proceedings of the 17th ACM Great Lakes symposium on VLSI, ACM, New York, NY, 2007, pp. 227–230.Google Scholar
  91. 91.
    M. Nicolaidis, A low-cost single-event latchup mitigation scheme, Proceedings of the 12th IEEE International On-Line Testing Symposium, 2006.Google Scholar
  92. 92.
    B.D. Olson, O.A. Amusan, S. Dasgupta, L.W. Massengill, A.F. Witulski, B.L. Bhuva, M.L. Alles, K.M. Warren, and D.R. Ball, Analysis of parasitic pnp bipolar transistor mitigation using well contacts in 130 nm and 90 nm cmos technology, IEEE Transactions on Nuclear Science 54 (2007), no. 4, 894–897.CrossRefGoogle Scholar
  93. 93.
    B. Osterloh, H. Michalik, S.A. Habinc, and B. Fiethe, Dynamic partial reconfiguration in space applications, NASA/ESA Conference on Adaptive Hardware and Systems, Athens, Piscataway, USA, 2009.Google Scholar
  94. 94.
    A.L.R. Pouponnot, Strategic use of see mitigation techniques for the development of the esa microprocessors: Past, present, and future, Proceedings of the 11th IEEE International On-Line Testing Symposium, French Rivieva, 2005, pp. 319–323.Google Scholar
  95. 95.
    D.K. Pradhan, Fault-tolerant computer system design, Prentice Hall PTR, Uppe Saddle River, NJ, 1996.Google Scholar
  96. 96.
    H. Quinn, P. Graham, J. Krone, M. Caffrey, and S. Rezgui, Radiation-induced multi-bit upsets in sram-based fpgas, IEEE Transactions on Nuclear Science 52 (2005), no. 6, 2455–2461.CrossRefGoogle Scholar
  97. 97.
    H. Quinn, K. Morgan, P. Graham, J. Krone, M. Caffrey, and K. Lundgreen, Domain crossing errors: Limitations on single device triple-modular redundancy circuits in xilinx fpgas, IEEE Transactions on Nuclear Science 54 (2007), no. 6, 2037–2043.CrossRefGoogle Scholar
  98. 98.
    S. Ramaswamy, Reconfigurable, high density, high speed, low power, radiation hardened fpga technology, Military and Aerospace Programmable Logic Devices (MAPLD) Conference, Amapolis, MD, 2008.Google Scholar
  99. 99.
    R.R. Rao, D. Blaauw, and D. Sylvester, Soft error reduction in combinational logic using gate resizing and flip-flop selection, IEEE International Conference on Computer-Aided Design, ICCAD, IEEE Society, San Jose, CA, 2006, pp. 502–509.Google Scholar
  100. 100.
    S. Rezgui, J.J. Wang, E.C. Tung, B. Cronquist, and J. McCollum, Comprehensive see characterization of 0.13 μ m flash-based fpgas by heavy ion beam test, Proceedings of the 9th European Conference on Radiation and Its Effects on Components and Systems, 2007, pp. 1–6.Google Scholar
  101. 101.
    S. Rezgui, J.J. Wang, Y. Sun, B. Cronquist, and J. McCollum, Configuration and routing effects on the set propagation in flash-based fpgas, IEEE Transactions on Nuclear Science 55 (Piscataway, USA, 2008), no. 6, 3328–3335.CrossRefGoogle Scholar
  102. 102.
    S. Rezgui, J.J. Wang, Yinming Sun, B. Cronquist, and J. McCollum, New reprogrammable and non-volatile radiation tolerant fpga: Rta3p, Aerospace Conference, 2008 IEEE, Big sky, MI 1-8 2008, pp. 1–11.Google Scholar
  103. 103.
    J.R. Schwank, M.R. Shaneyfelt, B.L. Draper, and P.E. Dodd, Busfet-a radiation-hardened soi transistor, IEEE Transactions on Nuclear Science 46 (1999), no. 6, 1809–1816.CrossRefGoogle Scholar
  104. 104.
    M.R. Shaneyfelt, P.E. Dodd, B.L. Draper, and R.S. Flores, Challenges in hardening technologies using shallow-trench isolation, IEEE Transactions on Nuclear Science 45 (1998), no. 6, 2584–2592.CrossRefGoogle Scholar
  105. 105.
    L. Singhal and E. Bozorgzadeh, Multi-layer floorplanning on a sequence of reconfigurable designs, Field Programmable Logic and Applications, 2006. FPL ’06. International Conference on, Madrid, 28–30 2006, pp. 1–8.Google Scholar
  106. 106.
    R.K. Smeltzer, Hole trap creation in sio2 by phosphorus ion penetration of polycrystalline silicon, IEEE Transactions on Nuclear Science 29 (1982), no. 6, 1467–1470.CrossRefGoogle Scholar
  107. 107.
    D. Soderman and Y. Panchul, Implementing c designs in hardware: A full-featured ansi c to rtl verilog compiler in action, Proceedings of the International Verilog HDL Conference and VHDL International Users Forum, Santa Clava, CA, 1998.Google Scholar
  108. 108.
    J.R. Srour and J.M. McGarrity, Radiation effects on microelectronics in space, Proceedings of the IEEE 76 (1988), no. 11, 1443–1469.CrossRefGoogle Scholar
  109. 109.
    D.L. Staebler and C.R. Wronski, Reversible conductivity changes in discharge-produced amorphous si, Applied Physics Letters 31 (1977), no. 4, 292–294.CrossRefGoogle Scholar
  110. 110.
    L. Sterpone, N. Battezzati, and V. Ferlet-Cavrois, Analysis of set propagation in flash-based fpgas by means of electrical pulse injection, IEEE 10th European Conference on Radiation Effects on Component and Systems , RADECS, IEEE Society, 2009, pp. B–3.Google Scholar
  111. 111.
    L. Sterpone and M. Violante, Analysis of the robustness of the tmr architecture in sram-based fpgas, IEEE Transactions on Nuclear Science 52 (Piscataway, USA, 2005), no. 5, 1545–1549.CrossRefGoogle Scholar
  112. 112.
    L. Sterpone and M. Violante, A new analytical approach to estimate the effects of seus in tmr architectures implemented through sram-based fpgas, IEEE Transactions on Nuclear Science 52 (2005), no. 6, 2217–2223.CrossRefGoogle Scholar
  113. 113.
    L. Sterpone and M. Violante, A new reliability-oriented place and route algorithm for sram-based fpgas, IEEE Transactions on Computers 55 (2006), no. 6, 732–744.CrossRefGoogle Scholar
  114. 114.
    E. Sun, J. Moll, J. Berger, and B. Alders, Breakdown mechanism in short-channel mos transistors, Electron Devices Meeting, 1978 International, vol. 24, 1978, pp. 478–482.Google Scholar
  115. 115.
    G.M. Swift, S. Rezgui, J. George, C. Carmichael, M. Napier, J. Maksymowicz, J. Moore, A. Lesea, R. Koga, and T.F. Wrobel, Dynamic testing of xilinx virtex-ii field programmable gate array (fpga) input/output blocks (iobs), IEEE Transactions on Nuclear Science 51 (Piscataway, USA, 2004), no. 6, 3469–3474.CrossRefGoogle Scholar
  116. 116.
    S.M. Sze and K.K. Ng, Physics of semiconductor devices, 2 ed., Wiley, New York, NY 2007.Google Scholar
  117. 117.
    T. Taghavi, S. Ghiasi, and M. Sarrafzadeh, Routing algorithms: architecture driven rerouting enhancement for fpgas, Proceedings of the IEEE International Symposium on Circuits and Systems, Island of kos 2006.Google Scholar
  118. 118.
    M.T. Takagi, I. Yoshii, N. Ikeda, H. Yasuda, and K. Hama, A highly reliable metal-to-metal antifuse for high-speed field programmable gate arrays, International Electron Devices Meeting Technical Digest, San Fransisco, CA, 1993, pp. 31–34.Google Scholar
  119. 119.
    H. Tan and R.F. DeMara, A physical resource management approach to minimizing fpga partial reconfiguration overhead, IEEE International Conference on Reconfigurable Computing and FPGA’s, San Luis Potosi, 2006.Google Scholar
  120. 120.
    S. Thakur, Y-W. Chang, D.F. Wong, and S. Muthukrishnan, Algorithms for an fpga switch module routing problem with application to global routing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16 (1997), no. 1, 32–46.CrossRefGoogle Scholar
  121. 121.
    Y.P. Tsividis, Operation and modeling of the mos transistor, McGraw-Hill, New York, NY, 1987.Google Scholar
  122. 122.
    R. Van Bentum and H. Vogt, Structural characterization of local simox-substrates, SOI Conference, 1998. Proceedings, 1998 IEEE International, Stuart, FL, 5–8 1998, pp. 49–50.Google Scholar
  123. 123.
    M. Vasilko, Dynasty: A temporal floorplanning based cad framework for dynamically reconfigurable logic systems, Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications, Glasgow, 1999, pp. 124–133.Google Scholar
  124. 124.
    S. Voldman, E. Gebreselasic, L. Lanzerotti, T. Larsen, N. Feilchenfeld, S. St. Onge, A. Joseph, and J. Dunn, The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness, Reliability Physics Symposium. Proceedings of the 43rd Annual 2005 IEEE International, Barcelona April 2005, pp. 112–120.Google Scholar
  125. 125.
    J.J. Wang, S. Samiee, H.-S. Chen, C.-K. Huang, M. Cheung, J. Borillo, S.-N. Sun, B. Cronquist, and J. McCollum, Total ionizing dose effects on flash-based field programmable gate array, IEEE Transactions on Nuclear Science 51 (2004), no. 6, 3759–3766.CrossRefGoogle Scholar
  126. 126.
    W. Wang, Rc hardened fpga configuration sram cell design, Electronics Letters 40 (2004), no. 9, 525–526.CrossRefGoogle Scholar
  127. 127.
    W. Wang and H. Gong, Edge triggered pulse latch design with delayed latching edge for radiation hardened application, IEEE Transactions on Nuclear Science 51 (2004), no. 2, 3626–3630.CrossRefMathSciNetGoogle Scholar
  128. 128.
    W.L. Warren, M.R. Shaneyfelt, D.M. Fleetwood, J.R. Schwank, P.S. Winokur, and R.A.B. Devine, Microscopic nature of border traps in mos oxides, IEEE Transactions on Nuclear Science 41 (1994), no. 6, 1817–1827.CrossRefGoogle Scholar
  129. 129.
    M. Watanabe and F. Kobayashi, Optically reconfigurable gate arrays vs. asics, Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 2006, pp. 1164–1167.Google Scholar
  130. 130.
    G. Wirth, F.L. Kastensmidt, and I. Ribeiro, Single event transients in logic circuits-load and propagation induced pulse broadening, IEEE Transactions on Nuclear Science 55 (2008), no. 6, 2928–2935.CrossRefGoogle Scholar
  131. 131.
    R.J. Wong and K.E. Gordon, Reliability mechanism of the unprogrammed amorphous silicon antifuse, Reliability Physics Symposium, 1994. Proceedings of the 32nd Annual Proceedings, IEEE International, San Jose, CA, 11–14 1994, pp. 378–382.Google Scholar
  132. 132.
    M.A. Xapsos, G.P. Summers, and E.M. Jackson, Enhanced total ionizing dose tolerance of bulk cmos transistors fabricated for enhanced total ionizing dose tolerance of bulk cmos transistors fabricated for ultra-low power application ultra-low power applications, IEEE Transactions on Nuclear Science 46 (1999), no. 6, 1697–1701.CrossRefGoogle Scholar
  133. 133.
    Xilinx, Planahead user guide, ug632 (v 11.4) ed., December 2009.Google Scholar
  134. 134.
    C.R. Yount and D.P. Siewiorek, A methodology for the rapid injection of transient hardware errors, IEEE Transactions on Computers 45 (1996), no. 8, 881–891zbMATHCrossRefGoogle Scholar
  135. 135.
    P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, Temporal floorplanning using the t-tree formulation, Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, Edinburg, 7–11 2004, pp. 300–305.Google Scholar
  136. 136.
    W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny, Evaluation of a non-volatile fpga based on mram technology, Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology, Piscataway, USA, 2006, pp. 1–4.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Niccolò Battezzati
    • 1
    Email author
  • Luca Sterpone
    • 2
  • Massimo Violante
    • 1
  1. 1.Dipto. Automatica e InformaticaPolitecnico di TorinoTorinoItaly
  2. 2.Politecnico di TorinoTorinoItaly

Personalised recommendations