Deterministic Test Generation Algorithms



The previous chapter provided an understanding of test generation and showed where and how test generation is used in digital system testing.


Test Generation Test Vector Fault Coverage Fault Simulation Primary Output 
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  1. 1.
    Roth JP (1966) Diagnosis of automata failures: a calculus and a method. IBM J Res Dev 10(4):278–291CrossRefGoogle Scholar
  2. 2.
    Roth JP, Bouricius WG, Schneider PR (1967) Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits. IEEE Trans Electron Comput EC-16(5):567–580CrossRefGoogle Scholar
  3. 3.
    Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C-30(3):215–222CrossRefGoogle Scholar
  4. 4.
    Fujiwara H (1985) FAN: A Fanout-oriented test pattern generation algorithm. In: Proceedings of the international symposium on circuits and systems, pp 671–674, July 1985Google Scholar
  5. 5.
    Fujiwara H, Shimono T (1983) On the acceleration of test generation algorithms. In: Proceedings of the international fault-tolerant computing symposium, pp 98–105, June 1983Google Scholar
  6. 6.
    Fujiwara H, Shimono T (1983) On the acceleration of test generation algorithms. IEEE Trans Comput C-32(12):1137–1144CrossRefGoogle Scholar
  7. 7.
    Schulz MH, Auth E (1988) Advanced automatic test pattern generation and redundancy identification techniques. In: Proceedings of the international fault-tolerant computing symposium, pp 30–35, June 1988Google Scholar
  8. 8.
    Schulz MH, Auth E (1989) Improved deterministic test pattern generation with applications to redundancy identification. IEEE Trans Comput-Aided Des 8(7):811–816CrossRefGoogle Scholar
  9. 9.
    Schulz MH,Trischler E, Serfert TM (1988) SOCRATES: A highly efficient automatic test pattern generation system. IEEE Trans Comput-Aid Des CAD-7(1):126–137CrossRefGoogle Scholar
  10. 10.
    Abramovici M, Breuer MA, Friedman AD (1994) Digital systems testing and testable design. IEEE Press, Piscataway, NJ. Revised printingCrossRefGoogle Scholar
  11. 11.
    Abramovici M, Menon PR, Miller DT (1984) Critical path tracing: an alternative to fault simulation. IEEE Des Test Comput 1(1):83–93CrossRefGoogle Scholar
  12. 12.
    Menon PR,Levendel YH, Abramovici M (1988) Critical path tracing in sequential circuits. In: Proceedings of the international conference on computer-aided design, pp 162–165, Nov. 1988Google Scholar
  13. 13.
    Menon PR,Levendel YH, Abramovici M (1991) SCRIPT: A critical path tracing algorithm for synchronous sequential circuits. IEEE Trans Comput-Aided Des 10(6):738–747CrossRefGoogle Scholar
  14. 14.
    Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, DordechtGoogle Scholar
  15. 15.
    Miczo A (2003) Digital logic testing and simulation, 2nd Ed. Wiley, New YorkCrossRefGoogle Scholar
  16. 16.
    Jha N, Gupta S (2003) Testing of digital systems. Cambridge University Press, CambridgeCrossRefGoogle Scholar
  17. 17.
    Pomeranz I, Reddy SM (1996) On static compaction of test sequences for synchronous sequential circuits. Proceedings of third design automation conference, pp 215–220Google Scholar
  18. 18.
    Nsiao MS, Rudnick EM, Patel JH (1997) Fast algorithms for static compaction of sequential circuit test vector. Proceedings of 15th IEEE VLSI test symposium, pp. 188–195Google Scholar
  19. 19.
    Hamzaoglu I, Patel JH (2000) Test set compaction algorithm for combinational circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 19(8):957–963CrossRefGoogle Scholar
  20. 20.
    Rudnick EM, Patl JH (1996) Simulation based techniques for dynamic test sequence compaction. IEEE/ACM international conference on computer aided design, pp 67–73Google Scholar
  21. 21.
    Niermann TM,Roy RK,Patel JH, Abraham JA (1992) Test compaction for sequential circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 11(2):260–267CrossRefGoogle Scholar
  22. 22.
    Goel P, Rosales BC (1979) Test generation and dynamic compaction of tests. Proceedings of test conference, pp 189–192Google Scholar

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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of Electrical & Computer EngineeringWorcester Polytechnic InstituteWorcesterUSA

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