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Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges

Chapter

Abstract

This chapter provides a brief overview of the principles and challenges of ultra-low power circuit design in the subthreshold region of operation. Design principles at all levels of hierarchy, namely, devices, circuits, and architecture need to be evaluated for maximum power gains. Brief description of SRAM design techniques as well as alternative architectures for lower power has also been discussed.

Keywords

Leakage Power Subthreshold Slope SRAM Cell Subthreshold Region Power Delay Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The authors would like to acknowledge the contributions and helpful discussions with Prof Kaushik Roy, Mr. Sumeet Gupta, Mr. M. Hwang, and other members of the Nanoelectronics Research Lab in Purdue University.

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Global FoundriesFishkillUSA
  2. 2.Intel CorporationPortlandUSA

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