Abstract
In this chapter, the RISPP approach is benchmarked. The benchmark results for the individual parts of the run-time system and prototyping results for the RISPP architecture are already presented in Chap. 4 and in Sect. 5.5, respectively. The first section provides benchmarks for the entire RISPP approach for different architectural parameters. In addition, the RISPP approach is compared with state-of-the-art approaches.
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Notes
- 1.
A Virtex-II 3000 and 6000 were used to develop the first RISPP prototypes; however, this thesis only presents the results for the final prototype that uses a Virtex-4 LX 160.
- 2.
The smallest run-time reconfigurable element – a frame – spans the full FPGA height for Virtex-II devices.
- 3.
The LUTs have six inputs instead of four (Virtex-II and Virtex-4) and a frame spans 20 CLBs (16 for Virtex-4).
- 4.
Please note that the SI implementations for Molen were selected optimally, considering how the reconfigurable fabric should be shared among the SIs (that are demanded in the computational blocks of the benchmark application) and considering the actual SI execution frequencies, but not considering “when” and “how often” Molen might reconfigure the SIs. When provided with nine ACs, a Molen compiler may decide to use only eight of them; however, still Molen’s performance does not improve beyond six ACs, whereas RISPP achieves noticeably better performance when equipped with more ACs, providing up to 1.94× speedup in comparison to Molen’s fastest execution time.
- 5.
- 6.
Actually, their nonreconfigurable counterparts used by the ASIPs.
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© 2011 Springer Science+Business Media, LLC
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Bauer, L., Henkel, J. (2011). Benchmarks and Comparisons. In: Run-time Adaptation for Reconfigurable Embedded Processors. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7412-9_6
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DOI: https://doi.org/10.1007/978-1-4419-7412-9_6
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