Abstract
The previous chapters have introduced a multidimensional data flow model of computation that can represent complex image processing applications including (i) out-of-order communication, (ii) sliding windows, (iii) parallel data access, and (iv) control flow. Furthermore, it has been shown how it helps to verify applications on a high level of abstraction assuring bounded memory execution and how required communication buffer sizes can be determined automatically either by simulation or by polyhedral buffer analysis. Corresponding tradeoffs between the required computation logic of the used hardware accelerators and the communication buffers by which they are interconnected have been evaluated in Section 7.7.
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Notes
- 1.
Note that the rectangular memory model would show the same difficulties.
- 2.
In order to ease analysis, a pessimistic approximation is performed by omitting virtual border extension.
- 3.
On the other hand, Section 8.5.2 will show that less than 300–400 flip-flops and lookup tables are sufficient to synthesize a heavily pipelined high-speed multidimensional FIFO.
References
AutoPilot. http://www.autoesl.com/products.html
Piplib. http://www.piplib.org/
Agrawal, A., Bakshi, A., Davis, J., Eames, B., Ledeczi, A., Mohanty, S., Mathur, V., Neema, S., Nordstrom, G., Prasanna, V., Raghavendra, C., Singh, M.: MILAN: A model based integrated simulation framework for design of embedded systems. In: Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), pp. 82–93. Snowbird, UT, (2001)
Baradaran, N., Diniz, P.C.: A register allocation algorithm in the presence of scalar replacement for fine-grain configurable architectures. In: DATE ’05: Proceedings of the conference on Design, Automation and Test in Europe, pp. 6–11. IEEE Computer Society, Washington, DC, (2005)
Beux, S.L., Marquet, P., Dekeyser, J.L.: A design flow to map parallel applications onto FPGAs. In: 17th IEEE International Conference on Field Programmable Logic and Applications (FPL2007), pp. 605–608. Amsterdam, The Netherlands (2007)
Bijlsma, T., Bekooij, M.J.G., Smit, G.J.M., Jansen, P.G.: Efficient inter-task communication for nested loop programs on a multiprocessor system. In: Proceedings of the ProRISC 2007 Workshop, pp. 122–127. Utrecht, Technology Foundation, Veldhoven, The Netherlands (2007)
Bukhari, K.Z., Kuzmanov, G., Vassiliadis, S.: DCT and IDCT implementations on different FPGA technologies. In: Proceedings of ProRISC 2002, pp. 232–235. Veldhofen, Netherlands (2002)
Cockx, J., Denolf, K., Vanhoof, B., Stahl, R.: SPRINT: a tool to generate concurrent transaction-level models from sequential code. EURASIP J. Appl. Signal Process. 2007(1), 213–213 (2007)
Coussy, P.: Synthèse d’interface de communication pour les composants virtuels. Ph.D. thesis, Université de Bretagne Sud, Laboratoire d’Electronique des Systèmes Temps Réel (LESTER) (2003)
Feautrier, P.: Parametric integer programming. Oper. Res. 22(3), 243–268 (1988)
Ghosh, S., Venigalla, S., Bayoumi, M.: Design and implementation of a 2D-DCT architecture using coefficient distributed arithmetic. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI ’05), pp. 162–166. IEEE Computer Society, Washington, DC (2005)
Haubelt, C., Falk, J., Keinert, J., Schlichter, T., Streubühr, M., Deyhle, A., Hadert, A., Teich, J.: A SystemC-based design methodology for digital signal processing systems. EURASIP J. Embedded Syst. Special Issue Embedded Digital Signal Process. Syst. 2007, Article ID 47,580, 22 pages (2007)
Lawal, N., Thörnberg, B., O’Nils, M.: Address generation for FPGA RAMS for efficient implementation of real-time video processing systems. In: International Conference on Field Programmable Logic and Applications, pp. 136–141 (2005)
Norell, H., Lawal, N., O’Nils, M.: Automatic generation of spatial and temporal memory architectures for embedded video processing systems. EURASIP J. Embedded Syst. 2007, Article ID 75,368, 10 pages (2007)
Verdoolaege, S., Nikolov, H., Stefanov, T.: PN: a tool for improved derivation of process networks. EURASIP J. Embedded Syst. 2007(1), 19–19 (2007)
Xilinx: CORE Generator. http://www.xilinx.com/tools/coregen.htm. Accessed 19 Sep 2010
Xilinx: Virtex-4 Family Overview, 3.0 edn. (2007)
Yu, H., Leeser, M.: Optimizing data intensive window-based image processing on reconfigurable hardware boards. In: IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 491–496. Athens, Greece (2005). DOI 10.1109/SIPS.2005.1579918
Zissulescu, C., Kienhuis, B., Deprettere, E.: Communication synthesis in a multiprocessor environment. In: International Conference on Field Programmable Logic and Applications, pp. 360–365. Tampere, Finland (2005)
Zissulescu, C., Turjan, A., Kienhuis, B., Deprettere, E.: Solving out of order communication using CAM memory; an implementation. In: 13th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2002). Veldhoven, Netherlands (2002)
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Keinert, J., Teich, J. (2011). Communication Synthesis. In: Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7182-1_8
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