Skip to main content
SpringerLink
Log in
Book cover

Design of Image Processing Embedded Systems Using Multidimensional Data Flow pp 1–7Cite as

Introduction

  • Chapter

  • 902 Accesses

Part of the book series: Embedded Systems ((EMSY))

Abstract

In the last few years, the progress in the design of embedded systems has been driven by the continuous development of new semiconductor devices offering more functionality than previous generations. Especially image processing applications could profit from this trend, because they are typically computationally intensive. Consequently, modern embedded devices permit the real-time execution of complex applications that some years ago would have been challenging even for huge workstations. Due to this fact, new application domains emerged ranging from digital acquisition, manipulation, and projection of cinematographic movies, over new medical diagnosis technologies, to hundreds of powerful consumer devices handling various multi-media content including images, sound, or video.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. International technology roadmap for semiconductors – design. Tech. rep., International Technology Roadmap for Semiconductors (2007)

    Google Scholar 

  2. Adé, M.: Data memory minimization for synchronous dataflow graphs emulated on DSP-FPGA targets. Ph.D. thesis, Katholieke Universiteit Leuven (1996)

    Google Scholar 

  3. Adé, M., Lauwereins, R., Peperstraete, J.A.: Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets. In: DAC ’97: Proceedings of the 34th Annual Conference on Design Automation, pp. 64–69. ACM Press, New York, NY, (1997)

    Google Scholar 

  4. Beux, S.L., Marquet, P., Dekeyser, J.L.: A design flow to map parallel applications onto FPGAs. In: 17th IEEE International Conference on Field Programmable Logic and Applications (FPL2007), pp. 605–608. Amsterdam, The Netherlands (2007)

    Google Scholar 

  5. Bhattacharyya, S., Murthy, P., Lee, E.: APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations. In: Design Automation for Embedded Systems, pp. 33–60. Kluwer Academic Publishers, Boston, MA (1997)

    Google Scholar 

  6. Bilsen, G., Engels, M., Lauwereins, R., Peperstraete, J.: Cyclo-static dataflow. IEEE Trans. Signal Process. 44(2), 397–408 (1996)

    Article  Google Scholar 

  7. Buck, J., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: A framework for simulating and prototyping heterogenous systems. Int. J. Comput. Simulat. 4(2), 155–182 (1994)

    Google Scholar 

  8. Calvez, J.P., Perrier, V.: MPEG-2 encoder-decoder illustrative example. Tech. rep., CoFluent Design (2005)

    Google Scholar 

  9. Cong, J., Han, G., Jiang, W.: Synthesis of an application-specific soft multiprocessor system. In: Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays (FPGA’07), pp. 99–107. ACM Press, New York, NY (2007)

    Google Scholar 

  10. Coussy, P.: Synthèse d’interface de communication pour les composants virtuels. Ph.D. thesis, Université de Bretagne Sud, Laboratoire d’Electronique des Systèmes Temps Réel (LESTER) (2003)

    Google Scholar 

  11. Dömer, R., Gerstlauer, A., Peng, J., Shin, D., Cai, L., Yu, H., Abdi, S., Gajski, D.D.: System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design. EURASIP J. Embedded Syst. 2008(647953), 13 (2008)

    Google Scholar 

  12. Engels, M., Bilsen, G., Lauwereins, R., Peperstraete, J.: Cyclo-static data flow: Model and implementation. In: Proceedings of the 28th Asilomar Conference on Signals, Systems, and Computers, pp. 503–507. Pacific Grove, CA (1994)

    Google Scholar 

  13. Forte Design Systems: Forte cynthesizer. http://www.forteds.com (2010). Accessed 25 Sep 2010

  14. Geilen, M., Basten, T., Stuijk, S.: Minimising buffer requirements of synchronous dataflow graphs with model checking. In: DAC ’05: Proceedings of the 42nd Annual Conference on Design Automation, pp. 819–824. ACM Press, New York, NY (2005)

    Google Scholar 

  15. Ghamarian, A., Geilen, M., Stuijk, S., Basten, T., Moonen, A., Bekooij, M., Theelen, B., Mousavi, M.: Throughput analysis of synchronous data flow graphs. In: Proceedings of the 6th International Conference on Application of Concurrency to System Design (ACSD’06), pp. 25–36. IEEE Computer Society, Washington, DC (2006)

    Google Scholar 

  16. Govindarajan, R., Gao, G., Desai, P.: Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks. J. VLSI Signal Process. 31, 207–229. Kluwer, Dordrecht (2002)

    Article  MATH  Google Scholar 

  17. Guillou, A.C., Quinton, P., Risset, T.: Hardware synthesis for multi-dimensional time. Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 40–50. The Hague, The Netherlands (2003)

    Google Scholar 

  18. Gupta, S., Gupta, R.K., Dutt, N.D., Nicolau, A.: Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Trans. Des. Autom. Electron. Syst. 9(4), 441–470 (2004)

    Article  Google Scholar 

  19. Ha, S., Kim, S., Lee, C., Yi, Y., Kwon, S., Joo, Y.P.: PeaCE: A hardware-software codesign environment for multimedia embedded systems. ACM Trans. Des. Autom. Electron. Syst. 12(3), 1–25 (2007)

    Article  Google Scholar 

  20. Hannig, F., Ruckdeschel, H., Dutta, H., Teich, J.: PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications. In: Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Lecture Notes in Computer Science (LNCS), pp. 287–293. Springer, London, United Kingdom (2008)

    Google Scholar 

  21. Harel, D.: Algorithmics: The Spirit of Computing, vol. 2nd edition. Addison-Wesley, Harlow, England (1992)

    Google Scholar 

  22. Haubelt, C., Falk, J., Keinert, J., Schlichter, T., Streubühr, M., Deyhle, A., Hadert, A., Teich, J.: A SystemC-based design methodology for digital signal processing systems. EURASIP J. Embedded Syst. Special Issue Embedded Digital Signal Process. Syst. 2007, Article ID 47,580, 22 pages (2007)

    Google Scholar 

  23. Impulse Accelerated Technologies: ImpulseC. http://www.impulsec.com/ (2010)

  24. Jung, H., Ha, S.: Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis. In: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS ’04), pp. 24–29. IEEE Computer Society, Washington, DC (2004)

    Google Scholar 

  25. Keinert, J., Falk, J., Haubelt, C., Teich, J.: Actor-oriented modeling and simulation of sliding window image processing algorithms. In: Proceedings of the 2007 IEEE/ACM/IFIP Workshop of Embedded Systems for Real-Time Multimedia (ESTIMEDIA 2007), pp. 113–118. Salzburg, Austria (2007)

    Google Scholar 

  26. Keinert, J., Haubelt, C., Teich, J.: Modeling and analysis of windowed synchronous algorithms. ICASSP2006 III, 892–895 (2006)

    Google Scholar 

  27. Keinert, J., Streubühr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., Teich, J., Meredith, M.: SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. Des. Autom. Electron. Syst. 14(1), 1–23 (2009)

    Article  MATH  Google Scholar 

  28. Lauwereins, R., Engels, M., Ade, M., Peperstraete, J.: Grape-II: a system-level prototyping environment for DSP applications. Computer 28(2), 35–43 (1995)

    Article  Google Scholar 

  29. Lawal, N., O’Nils, M., Thörnberg, B.: C++ based system synthesis of real-time video processing systems targeting FPGA implementation. In: IPDPS, pp. 1–7 (2007)

    Google Scholar 

  30. Lee, E.A., Messerschmitt, D.G.: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. Comput. C-36(1), 24–35 (1987)

    Article  Google Scholar 

  31. MathWorks, T.: Simulink. www.mathworks.com/products/simulink/ (2010)

  32. Mentor Graphics: Catapult C. http://www.mentor.com/products/esl/high_level_synthesis/catapult_synthesis/ (2010)

  33. Murthy, P.K.: Scheduling techniques for synchronous and multidimensional synchronous dataflow. Ph.D. thesis, University of California at Berkeley (1996)

    Google Scholar 

  34. Murthy, P.K., Lee, E.A.: On the optimal blocking factor for blocked, non-overlapped schedules. In: 28th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1052–1057. IEEE CS Press. Pacific Grove, CA (1994)

    Google Scholar 

  35. Oh, H., Ha, S.: Memory-optimized software synthesis from dataflow program graphs with large size data samples. EURASIP J. Appl. Signal Process. 2003(1), 514–529 (2003)

    MATH  Google Scholar 

  36. Parks, T.M., Pino, J.L., Lee, E.A.: A comparison of synchronous and cycle-static dataflow. In: ASILOMAR ’95: Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set), p. 204. IEEE Computer Society, Washington, DC (1995)

    Google Scholar 

  37. Stuijk, S., Geilen, M., Basten, T.: Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs. In: Proceedings of the 43rd Annual Conference on Design Automation (DAC ’06), pp. 899–904. ACM Press, New York, NY (2006)

    Google Scholar 

  38. Teich, J., Zitzler, E., Bhattacharyya, S.: Optimized software synthesis for digital signal processing algorithms: an evolutionary approach. In: IEEE Workshop on Signal Processing Systems, pp. 589–598. Boston, MA (1998)

    Google Scholar 

  39. Teich, J., Zitzler, E., Bhattacharyya, S.S.: Buffer memory optimization in DSP applications — an evolutionary approach. In: Fifth International Conference on Parallel Problem Solving from Nature (PPSN-V), pp. 885–894. Springer, Berlin, Germany (1998)

    Google Scholar 

  40. Thompson, M., Nikolov, H., Stefanov, T., Pimentel, A.D., Erbas, C., Polstra, S., Deprettere, E.F.: A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. In: Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS ’07), pp. 9–14. ACM Press, New York, NY (2007)

    Google Scholar 

  41. Wiggers, M., Bekooij, M., Jansen, P., Smit, G.: Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure. In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS ’06), pp. 10–15. ACM Press, New York, NY (2006)

    Google Scholar 

  42. Yang, H., Jung, H., Ha, S.: Buffer minimization in RTL synthesis from coarse-grained dataflow specification. In: SASMI. Nagoya, Japan (2006)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Michaelstraße 40, D-90425, Nürnberg, Germany

    Joachim Keinert

  2. Department of Computer Science 12, University of Erlangen-Nuremberg, Am Weichselgarten 3, D-91058, Erlangen, Germany

    Jürgen Teich

Authors
  1. Joachim Keinert
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jürgen Teich
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Joachim Keinert .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Keinert, J., Teich, J. (2011). Introduction. In: Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7182-1_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7182-1_1

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-7181-4

  • Online ISBN: 978-1-4419-7182-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation