Abstract
As the concept of cloud computing is gaining popularity, more data centers are built to support the needs. The data centers, which have consumed 1.5% of the total electrical energy generated in the USA in 2006, are paying the majority of their maintenance cost to the electricity bills. Reducing power consumption in the data centers is now a must not only for seizing sustainable development but also for preserving our planet green. Along the effort of building power-efficient data centers, this chapter will start by answering the ultimate question—where did the power go? By taking a top–down approach from the data center level all the way down to the microarchitectural level, this chapter visualizes the power breakdowns and discusses the power optimization techniques for each layer.
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- 1.
In DRAM, a rank is uniquely addressable 64 bits or 72 bits (when supporting 8 bits error correction code) data area. In a dual rank memory module, for example, memory controller uses chip select signal to choose what rank to access. In other words, the memory controller can access only half of the entire memory space in a cycle.
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Yeo, S., Lee, HH.S. (2012). Peeling the Power Onion of Data Centers. In: Joshi, Y., Kumar, P. (eds) Energy Efficient Thermal Management of Data Centers. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7124-1_3
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