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Soft Errors in Modern Electronic Systems pp 203–252Cite as

Circuit-Level Soft-Error Mitigation

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 41))

Abstract

In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern in the past for space applications, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEUs) affecting memory cells, latches, and flip-flops, and single-event transients (SETs) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this chapter, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.

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Notes

  1. 1.

    The implementation of the circuit and the evaluation of the technique are done by Thierry Bonnoit, Ph.D. student at TIMA lab.

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  1. TIMA Laboratory (CNRS, Grenoble INP, UJF), Grenoble, France

    Michael Nicolaidis

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  1. Grenoble INP, CNRS, UJF, TIMA Laboratory, av. Felix Viallet 46, Grenoble CX, 38031, France

    Michael Nicolaidis

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Nicolaidis, M. (2011). Circuit-Level Soft-Error Mitigation. In: Nicolaidis, M. (eds) Soft Errors in Modern Electronic Systems. Frontiers in Electronic Testing, vol 41. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6993-4_8

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