Abstract
Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores that are not used in an application can be shutdown, while the other islands can still be operational. When one or more of the islands are shutdown, the interconnect should allow the communication between islands that are operational. For this, the NoCs has to be designed efficiently to allow shutdown of VIs, thereby reducing the leakage power consumption. In this chapter, we present methods to design NoC topologies that provide such a support for both 2D and 3D ICs. We show how the concept of VIs need to be considered during topology synthesis phase itself. We also make studies to show the benefits of migrating to 3D-stacked chips for realistic applications that have multiple VIs.
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References
T. Ahonen, D. Signza-Tortosa, H. Bin, J. Nurmi, Topology Optimization for Application Specific Networks on Chip, Proceedings of SLIP, pp. 53–60, Feb 2004
K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, 3-D ICs: A Novel Chip Design for Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceedings of the IEEE, 89(5):602, 2001
E. Beigne, P. Vivet, Design of On-Chip and Off-Chip Interfaces for a GALS NoC Architecture, Proceedings 12th IEEE Intl Symposium on Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 172–181
E. Beigne, F. Clermidy, S. Miermont, P. Vivet, Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 129–138, April 07–10, 2008
L. Benini, G. De Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computers, pp.70–78, Jan 2002
E. Beyne, The Rise of the 3rd Dimension for System Intergration, Interconnect Technology Conference, 2006 International, pp. 1–5
T. Bjerregaard, S. Mahadevan, R. G. Olsen, J. Sparsoe, An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip, Proceedings 2005 International Symposium on 17-17 Nov 2005 pp. 171–174
A. P. Chandrakasan, S. Sheng, R.W. Brodersen, Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, 27(4):473–484, 1992
J. Cong, J. Wei, Y. Zhang, A Thermal-Driven Floorplanning Algorithm for 3D ICs, ICCAD, Nov 2004, pp. 306–313
G. De Micheli, L. Benini, Networks on Chips: Technology and Tools, Morgan Kaufmann, CA, First Edition, July 2006
T. Dumitras, S. Kerner, R. Marculescu, Towards on-chip fault-tolerant communication, ASPDAC 2003, pp. 225–232
F. Fallah and M. Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE Trans. on Electronics, pp. 509–519, Apr 2005
B. Goplen and S. Sapatnekar, Thermal Via Placement in 3D ICs, Proceedings of the International Symposium on Physical Design, p. 167, 2005
P. Guerrier, A. Greiner, A Generic Architecture for On-Chip Packet Switched Interconnections, Proceedings of the Conference on Design, Automation and Test in Europe, pp. 250–256, March 2000
A. Hansson, K. Goossens, A. Radulescu, A Unified Approach to Mapping and Routing on a Combined Guaranteed Service and Best-Effort Network-on-Chip Architectures, Technical Report No: 2005/00340, Philips Research, April 2005
W. H. Ho, T. M. Pinkston, A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns, HPCA, 2003
J. Hu, R. Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the Conference on Design, Automation and Test in Europe. March 2003, pp. 10688–106993
W.-L. Hung, G. M. Link, Y. Xie, N. Vijakrishnan, M. J. IRwin: Interconnect and Thermal-Aware Floorplanning for 3D Microprocessors, Proceedings of the ISQED, March 2006, pp.98–104
IBM ASIC Solutions, http://www-03.ibm.com/technology/asic/index.html
D. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gouls, J. M. Cohn, Managing power and performance for System-on-Chip designs using Voltage Islands, Proceedings of the ICCAD 2002, pp. 195–202
K. Lahiri, A. Raghunathan, S. Dey, Design Space Exploration for Optimizing On-Chip Communication Architectures, IEEE TCAD, 23(6):952–961, 2004
L. Leung, C. Tsui, Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands, Proceedings of DAC 2007, pp. 128–131
S. K. Lim, Physical Design for 3D System on Package, IEEE Design and Test of Computers, 22(6):532–539, 2005
I. Loi, F. Angiolini, L. Benini, Supporting Vertical Links for 3D Networks On Chip: Toward an Automated Design and Analysis Flow, Proceedings of Nanonets 2007, pp. 23–27
Q. Ma, E. F. Y. Young, Voltage Island Driven Floorplanning, Proceedings of ICCAD 2007, pp.644–649
I. Miro-Panades, et al., Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture, Networks-on-Chip, 2008. Second ACM/IEEE International Symposium on 7–10 April 2008 pp. 139–148
S. Murali, G. De Micheli, Bandwidth Constrained Mapping of Cores on to NoC Architectures, Proceedings of the Conference on Design, Automation and Test in Europe, 2004, pp. 20896–20902
S. Murali, G. De Micheli, SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs, Proceedings of the DAC 2004, pp. 914–919
S. Murali, T. Theocharides, N. VijayKrishnan, M. J. Irwin, L. Benini, G. De Micheli, Analysis of Error Recovery Schemes for Networks-on-Chips, IEEE Design and Test of Computers, 22(5):434–442, Sep–Oct 2005
S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, L. Raffo, Designing Application-Specific Networks on Chips with Floorplan Information, ICCAD 2006, pp. 355–362
S. Murali, C. Seiculescu, L. Benini, G. De Micheli, Synthesis of Networks on Chips for 3D Systems on Chips. ASPDAC 2009, pp. 242–247
U. Y. Ogras, R. Marculescu, P. Choudhary, D. Marculescu, Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip, Proceedings of DAC, June 2007
S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of DAC, pp. 65–70 June 2005
A. Pinto, L. Carloni, A. Sangiovanni-Vincentelli, Constraint-Driven Communication Synthesis, Proceedings of DAC, pp. 783–788, June 2002
K. Ryu, V. Mooney, Automated Bus Generation for Multiprocessor SoC Design, Proceedings of the Conference on Design, Automation and Test in Europe, pp. 282–287, March 2003
A. Sathanur, L. Benini, A. Macii, E. Macii, M. Poncino, Multiple Power-Gating Domain (multi-VGND) Architecture for Improved Leakage Power Reduction, Proceedings of ISLPED 2008, pp. 51–56
C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs. In Proceedings of the 46th Annual Design Automation Conference (DAC 2009), pp. 822–825, 2009
C. Seiculescu, S. Murali, L. Benini, G. De Micheli, SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip, 2009, pp. 9–14
K. Srinivasan, K. S. Chatha, G. Konjevod, An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks, Proceedings of ICCAD 2005, pp. 231–237
S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, G. De Micheli, × pipesLite: A Synthesis Oriented Design Library for Networks on Chips, Proceedings of the Conference on Design, Automation and Test in Europe 2005, pp. 1188–1193
Y-F. Tsai, D. Duarte, N. Vijaykrishnan, M.J. Irwin, Implications of Technology Scaling on Leakage Reduction Techniques, DAC 2003
R. Weerasekara, L.-R. Zeng, D. Pamunuwa, H. Tenhunen, Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs, Proceedings of ICCAD, 2007, pp. 212–219
J. Xu, W. Wolf, J. Henkel, S. Chakradhar, A Design Methodology for Application-Specific Networks-On-Chip, ACM Transactions on Embedded Computing Systems (TECS), 5(2): 263–280, 2006
P. Zhou, Y. Ma, Z. Li, R. P. Dick, L. Shang, H. Zhou, X. Hong, Q. Zhou, 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits, ICCAD, Nov 2007, pp. 590–597
X. Zhu, S. Malik, A Hierarchical Modeling Framework for On-Chip Communication Architectures, ICCD 2002, pp. 663–671, Nov 2002
Acknowledgements
We would like to acknowledge the financial contribution of CTI under project 10046.2 PFNM-NM and the ARTIST-DESIGN Network of Excellence.
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Seiculescu, C., Murali, S., Benini, L., Micheli, G.D. (2011). Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_8
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