Abstract
Leakage power has already been consuming a considerable portion of the active power in recent process technologies. In this chapter, we survey various power gating techniques to reduce the leakage power of on-chip routers. Then we introduce a run-time fine-grained power-gating router, in which power supply to each router component (e.g., virtual-channel buffer, crossbar’s multiplexer, and output latch) can be individually controlled in response to the applied workload. The fine-grained power gating router with 35 micro-power domains is designed using a commercial 65 nm process and evaluated in terms of the area overhead, application performance, and leakage power reduction.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
We selected a low-power CMOS process whose leakage power is quite small, since our final goal is to develop ultra low leakage on-chip networks.
References
Agarwal, N., Peh, L.S., Jha, N.: Garnet: A Detailed Interconnection Network Model Inside a Full-System Simulation Framework. Tech. Rep. CE-P08-001, Princeton University (2008)
Banerjee, A., Mullins, R., Moore, S.: A Power and Energy Exploration of Network-on-Chip Architectures. In: Proceedings of the International Symposium on Networks-on-Chip (NOCS’07), pp. 163–172 (2007)
Beigne, E., Clermidy, F., Lhermet, H., Miermont, S., Thonnart, Y., Tran, X.T., Valentian, A., Varreau, D., Vivet, P., Popon, X., Lebreton, H.: An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE Journal of Solid-State Circuits 44(4), 1167–1177 (2009)
Chen, X., Peh, L.S.: Leakage Power Modeling and Optimization in Interconnection Networks. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03), pp. 90–95 (2003)
Dally, W.J.: Virtual-Channel Flow Control. IEEE Transactions on Parallel and Distributed Systems 3(2), 194–205 (1992)
Galles, M.: Spider: A High Speed Network Interconnect. IEEE Micro 17(1), 34–39 (1997)
Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural Techniques for Power Gating of Execution Units. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’04), pp. 32–37 (2004)
IEEE Standard for Design and Verification of Low Power Integrated Circuits. IEEE Computer Society (2009)
Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M., Kondo, M.: Geyser-1: A MIPS R3000 CPU Core with Fine Grain Runtime Power Gating. In: Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC’09) (2009)
Ishikawa, M., Kamei, T., Kondo, Y., Yamaoka, M., Shimazaki, Y., Ozawa, M., Tamaki, S., Furuyama, M., Hoshi, T., Arakawa, F., Nishii, O., Hirose, K., Yoshioka, S., Hattori, T.: A 4500 MIPS/W, 86 μA Resume-Standby, 11 μA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Transactions on Electronics E88-C(4), 528–535 (2005)
Kanno, Y., et al.: Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. In: Proceedings of the International Solid-State Circuits Conference (ISSCC’06), pp. 2200–2209 (2006)
Kim, C., Burger, D., Keckler, S.W.: An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches. In: Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’02), pp. 211–222 (2002)
Magnusson, P.S., et al.: Simics: A Full System Simulation Platform. IEEE Computer 35(2), 50–58 (2002)
Martin, M.M.K., Hill, M.D., Wood, D.A.: Token Coherence: Decoupling Performance and Correctness. In: Proceedings of the International Symposium on Computer Architecture (ISCA’03), pp. 182–193 (2003)
Martin, M.M.K., Sorin, D.J., Beckmann, B.M., Marty, M.R., Xu, M., Alameldeen, A.R., Moore, K.E., Hill, M.D., Wood, D.A.: Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset. ACM SIGARCH Computer Architecture News (CAN’05) 33(4), 92–99 (2005)
Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In: Proceedings of the International Symposium on Networks-on-Chip (NOCS’08), pp. 23–32 (2008)
Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’08), pp. 55–60 (2008)
Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.: Prediction Router: Yet Another Low Latency On-Chip Router Architecture. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’09), pp. 367–378 (2009)
Mullins, R., West, A., Moore, S.: Low-Latency Virtual-Channel Routers for On-Chip Networks. In: Proceedings of the International Symposium on Computer Architecture (ISCA’04), pp. 188–197 (2004)
Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Kashima, T., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M., Nakamura, H.: A Fine-Grain Dynamic Sleep Control Scheme in MIPS R3000. In: Proceedings of the International Conference on Computer Design (ICCD’08), pp. 612–617 (2008)
Shang, L., Peh, L.S., Jha, N.K.: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA’03), pp. 79–90 (2003)
Soteriou, V., Peh, L.S.: Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks. IEEE Transactions on Parallel and Distributed Systems 18(3), 393–408 (2007)
Stine, J.M., Carter, N.P.: Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. IEEE Computer Architecture Letters 3(1), 14–17 (2004)
Usami, K., Ohkubo, N.: A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. In: Proceedings of the International Conference on Computer Design (ICCD’06) (2006)
Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.: An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits 43(1), 29–41 (2008)
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: SPLASH-2 Programs: Characterization and Methodological Considerations. In: Proceedings of the International Symposium on Computer Architecture (ISCA’95), pp. 24–36 (1995)
Acknowledgements
This research was performed by the authors for STARC as part of the Japanese Ministry of Economy, Trade and Industry sponsored “Next-Generation Circuit Architecture Technical Development” program. The authors thank VLSI Design and Education Center (VDEC) and Japan Science and Technology Agency (JST) CREST for their support.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Matsutani, H., Koibuchi, M., Nakamura, H., Amano, H. (2011). Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_2
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6911-8_2
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-6910-1
Online ISBN: 978-1-4419-6911-8
eBook Packages: EngineeringEngineering (R0)