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RF-Interconnect for Future Network-On-Chip

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Low Power Networks-on-Chip

Abstract

In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). It is projected that communication via NoC is one of the primary limiters to both performance and power consumption. To mitigate such problems, we explore the use of multiband RF-interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission and reconfigurable bandwidth. At the same time, we investigate the CMOS mixed-signal circuit implementation challenges for improving the RF-I signaling integrity and efficiency. Furthermore, we propose a micro-architectural framework that can be used to facilitate the exploration of scalable low power NoC architectures based on physical planning and prototyping.

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Acknowledgements

The authors would like to thank the US DARPA and GSRC for their contract supports and TAPO/IBM for their foundry service.

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Authors and Affiliations

  1. Electrical Engineering Department, University of California, Los Angeles, Engineering IV Building, Los Angeles, CA, 90095, USA

    Sai-Wang Tam

Authors
  1. Sai-Wang Tam
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  2. Eran Socher
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  3. Mau-Chung Frank Chang
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  4. Jason Cong
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  5. Glenn D. Reinman
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Corresponding author

Correspondence to Sai-Wang Tam .

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Editors and Affiliations

  1. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Cristina Silvano

  2. NEC Laboratories America, Inc., Independence Way 4, Princeton, 08540, New Jersey, USA

    Marcello Lajolo

  3. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Gianluca Palermo

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Tam, SW., Socher, E., Chang, MC.F., Cong, J., Reinman, G.D. (2011). RF-Interconnect for Future Network-On-Chip. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_10

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  • DOI: https://doi.org/10.1007/978-1-4419-6911-8_10

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