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On-Chip Interconnect with aelite

Part of the book series: Embedded Systems ((EMSY))

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Abstract

After completing our detailed exposition of the proposed on-chip interconnect, we now look at related work, and how they address the requirements from Chapter 1. Throughout this chapter, we highlight the contributions of our proposed interconnect and how it compares to the related works. For a more detailed exposition of the key concepts, we refer back to Chapter 2.

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Notes

  1. 1.

    A globally asynchronous implementation of our proposed router network is possible [52, 78] without any change to the concepts, but the uncertainty pertains the length of a slot (in absolute time), determined by all the routers together.

References

  1. Abeni L, Buttazzo G (2004) Resource reservation in dynamic real-time systems. Real-Time Systems 27(2):123–167

    Article  MATH  Google Scholar 

  2. ARINC653 (1997) ARINC Specification 653. Avionics Application Software Standard Interface

    Google Scholar 

  3. Bartic T, Desmet D, Mignolet JY, Marescaux T, Verkest D, Vernalde S, Lauwereins R, Miller J, Robert F (2004) Network-on-chip for reconfigurable systems: from high-level design down to implementation. In: Proc. FPL

    Google Scholar 

  4. Beigne E, Clermidy F, Vivet P, Clouard A, Renaudin M (2005) An asynchronous NOC architecture providing low latency service and its multi-level design framework. In: Proc. ASYNC

    Google Scholar 

  5. Beigné E, Clermidy F, Miermont S, Vivet P (2008) Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC. In: Proc. NOCS

    Google Scholar 

  6. Bekooij M, Moreira O, Poplavko P, Mesman B, Pastrnak M, van Meerbergen J (2004) Predictable embedded multiprocessor system design. LNCS 3199:77–91

    Google Scholar 

  7. Bekooij MJG, Smit GJM (2007) Efficient computation of buffer capacities for cyclo-static dataflow graphs. In: Proc. DAC

    Google Scholar 

  8. Benini L (2006) Application specific NoC design. In: Proc. DATE

    Google Scholar 

  9. Benini L, de Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Computer 35(1):70–80

    Article  Google Scholar 

  10. Bertozzi D, Jalabert A, Murali S, Tamhankar R, Stergiou S, Benini L, Micheli GD (2005) NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Transactions on Parallel and Distributed Systems 16(2):113–129

    Article  Google Scholar 

  11. Bjerregaard T, Sparsø J (2005) A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In: Proc. DATE

    Google Scholar 

  12. Bjerregaard T, Sparsø J (2005) A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In: Proc. ASYNC

    Google Scholar 

  13. Bjerregaard T, Mahadevan S, Grøndahl Olsen R, Sparsø J (2005) An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip. In: Proc. SOC

    Google Scholar 

  14. Bjerregaard T, Stensgaard M, Sparsø J (2007) A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. In: Proc. DATE

    Google Scholar 

  15. Bril RJ, Hentschel C, Steffens EF, Gabrani M, van Loo G, Gelissen JH (2001) Multimedia QoS in consumer terminals. In: Proc. SiPS

    Google Scholar 

  16. van de Burgwal MD, Smit GJM, Rauwerda GK, Heysters PM (2006) Hydra: an energy-efficient and reconfigurable network interface. In: Proc. ERSA

    Google Scholar 

  17. Chen J, Jone W, Wang J, Lu HI, Chen T (1999) Segmented bus design for low-power systems. IEEE Transactions on VLSI 7(1):25–29

    Article  Google Scholar 

  18. Coenen M, Murali S, Rădulescu A, Goossens K, De Micheli G (2006) A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. In: Proc. CODES+ISSS

    Google Scholar 

  19. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proc. DAC

    Google Scholar 

  20. Dielissen J, Rădulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the Philips network-on-chip. In: IP-Based SOC Design

    Google Scholar 

  21. Dutta S, Jensen R, Rieckmann A (2001) Viper: a multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers 18(5):21–31

    Article  Google Scholar 

  22. Felicijan T (2007) Asynchronous tdma networks on chip. Tech. rep., Royal Philips Electronics

    Google Scholar 

  23. Gangwal O, Rădulescu A, Goossens K, Pestana S, Rijpkema E (2005) Building predictable systems on chip: an analysis of guaranteed communication in the Æthereal network on chip. In: Dynamic and Robust Streaming in and Between Connected Consumer-Electronics Devices, Kluwer, Dordrecht

    Google Scholar 

  24. Gangwal OP, Janssen J, Rathnam S, Bellers E, Duranto M (2003) Understanding video pixel processing applications for flexible implementations. In: Proc. DSD

    Google Scholar 

  25. Genko N, Atienza D, Micheli GD, Mendias J, Hermida R, Catthoor F (2005) A complete network-on-chip emulation framework. In: Proc. DATE

    Google Scholar 

  26. Gheorghita SV, Palkovic M, Hamers J, Vandecappelle A, Mamagkakis S, Basten T, Eeckhout L, Corporaal H, Catthoor F, Vandeputte F, De Bosschere K (2009) System-scenario-based design of dynamic embedded systems. ACM Transactions on Design Automation of Electronic Systems 13(1):1–45

    Article  Google Scholar 

  27. Goossens K, Dielissen J, Gangwal OP, González Pestana S, Rădulescu A, Rijpkema E (2005) A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: Proc. DATE

    Google Scholar 

  28. Goossens K, Dielissen J, Rădulescu A (2005) The Æthereal network on chip: concepts, architectures, and implementations. IEEE Design and Test of Computers 22(5):21–31

    Google Scholar 

  29. Graham R (1969) Bounds on multiprocessing timing anomalies. SIAM Journal of Applied Mathematics 17(2):416–429

    Article  MATH  Google Scholar 

  30. Guérin R, Orda A (2000) Networks with advance reservations: The routing perspective. In: Proc. INFOCOM

    Google Scholar 

  31. Guérin R, Orda A, Williams D (1997) QoS routing mechanisms and OSPF extensions. In: Proc. GLOBECOM

    Google Scholar 

  32. Halfhill TR (2006) Ambric’s new parallel processor. Microprocessor Report

    Google Scholar 

  33. Hansson A, Goossens K (2007) Trade-offs in the configuration of a network on chip for multiple use-cases. In: Proc. NOCS

    Google Scholar 

  34. Hansson A, Goossens K, Rădulescu A (2005) A unified approach to constrained mapping and routing on network-on-chip architectures. In: Proc. CODES+ISSS

    Google Scholar 

  35. Hansson A, Coenen M, Goossens K (2007) Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. In: Proc. CODES+ISSS

    Google Scholar 

  36. Hansson A, Coenen M, Goossens K (2007) Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. In: Proc. DATE

    Google Scholar 

  37. Hansson A, Goossens K, Rădulescu A (2007) Avoiding message-dependent deadlock in network-based systems on chip. VLSI Design 2007:1–10

    Google Scholar 

  38. Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2008) Applying dataflow analysis to dimension buffers for guaranteed performance in Networks on Chip. In: Proc. NOCS

    Google Scholar 

  39. Hansson A, Goossens K, Bekooij M, Huisken J (2009) Compsoc: a template for composable and predictable multi-processor system on chips. ACM Transactions on Design Automation of Electronic Systems 14(1):1–24

    Article  Google Scholar 

  40. Hansson A, Subburaman M, Goossens K (2009) Aelite: a flit-synchronous network on chip with composable and predictable services. In: Proc. DATE

    Google Scholar 

  41. Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2009) Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers and Design Techniques

    Google Scholar 

  42. Ho WH, Pinkston TM (2003) A methodology for designing efficient on-chip interconnects on well-behaved communication patterns. In: Proc. HPCA

    Google Scholar 

  43. Holzenspies P, Hurink J, Kuper J, Smit G (2008) Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip MPSoC. In: Proc. DATE, 10.1109/DATE.2008.4484628

    Google Scholar 

  44. Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27(5):51–61

    Article  Google Scholar 

  45. Hu J, Mărculescu R (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proc. ASP-DAC

    Google Scholar 

  46. Hu J, Mărculescu R (2003) Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. In: Proc. DATE

    Google Scholar 

  47. Jantsch A (2006) Models of computation for networks on chip. In: Proc. ACSD

    Google Scholar 

  48. Kang J, Henriksson T, van der Wolf P (2005) An interface for the design and implementation of dynamic applications on multi-processor architecture. In: Proc. ESTImedia

    Google Scholar 

  49. Kavaldjiev N (2006) A run-time reconfigurable network-on-chip for streaming DSP applications. PhD thesis, University of Twente

    Google Scholar 

  50. Kopetz H (1997) Real-Time Systems: Design Principles for Distributed Embedded Applications. Kluwer Academic Publishers, Dordrecht

    MATH  Google Scholar 

  51. Kopetz H, Bauer G (2003) The time-triggered architecture. Proceedings of the IEEE 91(1):112–126

    Article  Google Scholar 

  52. Kopetz H, El Salloum C, Huber B, Obermaisser R, Paukovits C (2008) Composability in the time-triggered system-on-chip architecture. In: Proc. SOCC

    Google Scholar 

  53. Kramer J, Magee J (1990) The evolving philosophers problem: dynamic change management. IEEE Transactions on Software Engineering 16(11):1293–1306,

    Article  Google Scholar 

  54. Krstić M, Grass E, Gürkaynak F, Vivet P (2007) Globally asynchronous, locally synchronous circuits: overview and outlook. IEEE Design and Test of Computers 24(5):430–441

    Article  Google Scholar 

  55. Leijten J, van Meerbergen J, Timmer A, Jess J (2000) Prophid: a platform-based design method. Journal of Design Automation for Embedded Systems 6(1):5–37

    Article  Google Scholar 

  56. Liang J, Swaminathan S, Tessier R (2000) aSOC: A scalable, single-chip communications architecture. In: Proc. PACT

    Google Scholar 

  57. Lickly B, Liu I, Kim S, D Patel H, Edwards SA, Lee EA (2008) Predictable programming on a precision timed architecture. In: Proc. CASES

    Google Scholar 

  58. Lu Z, Haukilahti R (2003) NOC application programming interfaces: high level communication primitives and operating system services for power management. In: Networks on Chip, Kluwer Academic Publishers, Dordrecht

    Google Scholar 

  59. Mangano D, Locatelli R, Scandurra A, Pistritto C, Coppola M, Fanucci L, Vitullo F, Zandri D (2006) Skew insensitive physical links for network on chip. In: Proc. NANONET

    Google Scholar 

  60. Marescaux T, Corporaal H (2007) Introducing the SuperGT network-on-chip. In: Proc. DAC

    Google Scholar 

  61. Marescaux T, Mignolet J, Bartic A, Moffat W, Verkest D, Vernalde S, Lauwereins R (2003) Networks on chip as hardware components of an OS for reconfigurable systems. In: Proc. FPL

    Google Scholar 

  62. Matta I, Bestavros A (1998) A load profiling approach to routing guaranteed bandwidth flows. In: Proc. INFOCOM

    Google Scholar 

  63. Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In: Proc. DATE

    Google Scholar 

  64. Miro Panades I, Greiner A (2007) Bi-synchronous FIFO for synchronous circuit communication well suited for network-on-chip in GALS architectures. In: Proc. NOCS

    Google Scholar 

  65. Moonen A (2004) Modelling and simulation of guaranteed throughput channels of a hard real-time multiprocessor system. Master’s thesis, Eindhoven University of Technology

    Google Scholar 

  66. Moraes F, Calazans N, Mello A, Möller L, Ost L (2004) HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration VLSI Journal 38(1):69–93

    Article  Google Scholar 

  67. Moreira O, Valente F, Bekooij M (2007) Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor. In: Proc. EMSOFT

    Google Scholar 

  68. Murali S, de Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proc. DATE

    Google Scholar 

  69. Murali S, de Micheli G (2004) SUNMAP: a tool for automatic topology selection and generation for NoCs. In: Proc. DAC

    Google Scholar 

  70. Murali S, De Micheli G (2005) An application-specific design methodology for STbus crossbar generation. In: Proc. DATE

    Google Scholar 

  71. Murali S, Benini L, de Micheli G (2005) Mapping and physical planning of networks on chip architectures with quality of service guarantees. In: Proc. ASP-DAC

    Google Scholar 

  72. Murali S, Coenen M, Rădulescu A, Goossens K, De Micheli G (2006) Mapping and configuration methods for multi-use-case networks on chips. In: Proc. ASP-DAC

    Google Scholar 

  73. Murali S, Coenen M, Rădulescu A, Goossens K, De Micheli G (2006) A methodology for mapping multiple use-cases on to networks on chip. In: Proc. DATE

    Google Scholar 

  74. Nesbit K, Moreto M, Cazorla F, Ramirez A, Valero M, Smith J (2008) Multicore resource management. IEEE Micro 28(3):6–16

    Article  Google Scholar 

  75. Nollet V, Marescaux T, Avasare P, Mignolet JY (2005) Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles. In: Proc. DATE

    Google Scholar 

  76. Ost L, Mello A, Palma J, Moraes F, Calazans N (2005) MAIA: a framework for networks on chip generation and verification. In: Proc. ASP-DAC

    Google Scholar 

  77. Palesi M, Holsmark R, Kumar S, Catania V (2009) Application specific routing algorithms for networks on chip. IEEE Transactions on Parallel and Distributed Systems 20(3):316–330

    Article  Google Scholar 

  78. Panades I, Greiner A, Sheibanyrad A (2006) A low cost network-on-chip with guaranteed service well suited to the GALS approach. In: Proc. NANONET

    Google Scholar 

  79. Paukovits C (2008) The time-triggered system-on-chip architecture. PhD thesis, Technische Universität Wien, Institut für Technische Informatik

    Google Scholar 

  80. Paukovits C, Kopetz H (2008) Concepts of switching in the time-triggered network-on-chip. In: Proc. RTCSA

    Google Scholar 

  81. PIBus (1994) PI-Bus Standard OMI 324. Siemens AG, ver. 0.3d edn

    Google Scholar 

  82. Pullini A, Angiolini F, Murali S, Atienza D, De Micheli G, Benini L (2007) Bringing NoCs to 65 nm. IEEE Micro 27(5):75–85

    Article  Google Scholar 

  83. Rajkumar R, Juvva K, Molano A, Oikawa S (1998) Resource kernels: a resource-centric approach to real-time systems. In: Proc. MMCN

    Google Scholar 

  84. Rijpkema E, Goossens K, Rădulescu A, Dielissen J, van Meerbergen J, Wielage P, Waterlander E (2003) Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proceedings Computers and Digital Techniques 150(5):294–302

    Article  Google Scholar 

  85. Rostislav D, Vishnyakov V, Friedman E, Ginosar R (2005) An asynchronous router for multiple service levels networks on chip. In: Proc. ASYNC

    Google Scholar 

  86. Rădulescu A, Dielissen J, Goossens K, Rijpkema E, Wielage P (2005) An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Transactions on CAD of Integrated Circuits and Systems pp. 4–17

    Google Scholar 

  87. Rumpler B (2006) Complexity management for composable real-time systems. In: Proc. ISORC

    Google Scholar 

  88. Rutten M, Pol EJ, van Eijndhoven J, Walters K, Essink G (2005) Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture. IS&T/SPIE Electron Imag 5683

    Google Scholar 

  89. Sgroi M, Sheets M, Mihal A, Keutzer K, Malik S, Rabaey J, Sangiovanni-Vincentelli A (2001) Addressing the system-on-a-chip interconnect woes through communication-based design. In: Proc. DAC

    Google Scholar 

  90. Smit LT, Smit GJM, Hurink JL, Broersma H, Paulusma D, Wolkotte PT (2004) Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture. In: Proc. FPT

    Google Scholar 

  91. Song YH, Pinkston TM (2000) On message-dependent deadlocks in multiprocessor/multicomputer systems. In: Proc. HiPC

    Google Scholar 

  92. SonicsMX (2005) SonicsMX Datasheet. Sonics, Inc. Available on www.sonicsinc.com

  93. Sriram S, Bhattacharyya S (2000) Embedded Multiprocessors: Scheduling and Synchronization. CRC Press, Boca Raton, FL

    Google Scholar 

  94. Stergiou S, Angiolini F, Carta S, Raffo L, Bertozzi D, de Micheli G (2005) × pipes Lite: a synthesis oriented design library for networks on chips. In: Proc. DATE

    Google Scholar 

  95. Stoica I, Zhang H (1999) Providing guaranteed services without per flow management. In: Proc. SIGCOMM

    Google Scholar 

  96. Stuijk S, Basten T, Geilen M, Ghamarian A, Theelen B (2008) Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip. Journal of Systems Architecture 54(3–4):411–426

    Article  Google Scholar 

  97. Weber WD, Chou J, Swarbrick I, Wingard D (2005) A quality-of-service mechanism for interconnection networks in system-on-chips. In: Proc. DATE

    Google Scholar 

  98. Wentzlaff D, Griffin P, Hoffmann H, Bao L, Edwards B, Ramey C, Mattina M, Miao CC, Brown JF, Agarwal A (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27(5):15–31

    Article  Google Scholar 

  99. Widyono R (1994) The design and evaluation of routing algorithms for real-time channels. Tech. Rep. TR-94-024, University of California at Berkeley & Int’l Comp. Sci. Inst.

    Google Scholar 

  100. Wielage P, Marinissen E, Altheimer M, Wouters C (2007) Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. In: Proc. DATE

    Google Scholar 

  101. Wiklund D, Liu D (2003) SoCBUS: switched network on chip for hard real time embedded systems. In: Proc. IPDPS

    Google Scholar 

  102. Wingard D (2004) Socket-based design using decoupled interconnects. In: Interconnect-Centric design for SoC and NoC, Kluwer, Dordrecht

    Google Scholar 

  103. Wingard D, Kurosawa A (1998) Integration architecture for system-on-a-chip design. In: Proc. CICC

    Google Scholar 

  104. Wolkotte P, Smit G, Rauwerda G, Smit L (2005) An energy-efficient reconfigurable circuit-switched network-on-chip. In: Proc. IPDPS

    Google Scholar 

  105. Wüst C, Steffens L, Verhaegh W, Bril R, Hentschel C (2005) QoS control strategies for high-quality video processing. Real-Time Systems 30(1):7–29

    Article  Google Scholar 

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  1. Research & Development ARM Ltd., Cambridge, UK

    Andreas Hansson

  2. Eindhoven University of Technology, Eindhoven, The Netherlands

    Kees Goossens

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Hansson, A., Goossens, K. (2011). Related Work. In: On-Chip Interconnect with aelite. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6865-4_9

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