Abstract
The complexity of system verification and integration is exploding due to the growing number of real-time applications integrated on a single chip. In addition, the applications have diverse requirements and behaviours and are started and stopped dynamically at run time. To reduce the design and verification complexity, it is crucial to offer a platform that enables independent implementation, verification and debugging of applications.
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References
Akesson B, Goossens K, Ringhofer M (2007) Predator: a predictable SDRAM memory controller. In: Proc. CODES+ISSS
Magarshack P, Paulin PG (2003) System-on-chip beyond the nanometer wall. In: Proc. DAC
Molnos A, Heijligers M, Cotofana S (2008) Compositional, dynamic cache management for embedded chip multiprocessors. In: Proc. DATE
Nollet V, Marescaux T, Avasare P, Mignolet JY (2005) Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles. In: Proc. DATE
Stiliadis D, Varma A (1998) Latency-rate servers: a general model for analysis of traffic scheduling algorithms. IEEE/ACM Transactions on Networking 6(5):611–624
van den Brand J, Bekooij M (2007) Streaming consistency: a model for efficient MPSoC design. In: Proc. DSD
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© 2011 Springer Science+Business Media, LLC
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Hansson, A., Goossens, K. (2011). Conclusions and Future Work. In: On-Chip Interconnect with aelite. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6865-4_10
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DOI: https://doi.org/10.1007/978-1-4419-6865-4_10
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