Abstract
ASIP exploration uses the mappability method for the selection of processor core and algorithm combinations for multi-core designs. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. This information is used for narrowing the exploration space of the subsequent ASIP design that exploits commercial ASIP design environment, Synopsys Processor Designer. According to simulation results the proposed ASIPs are able to achieve up to 96% of maximum performance with a clear reduction in complexity.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
K. Chen, S. Malik, and D. I. August. Retargetable static timing analysis for embedded software. In Proceedings of the 14th International Symposium on System Synthesis, pages 39–44, 2001.
N. Ghazal, R. Newton, and J. Rabaye. Retargetable estimation scheme for dsp architectures. In Asia and South Pacific Design Automation Conference, pages 485–489, 2000.
J. Gong, D. Gajski, and A. Nicolau. Performance evaluation for application-specific architectures. IEEE Transactions on VLSI, 3(4):483–490, December 1995.
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, Austin, TX, USA, December 2001.
J. Kreku and J.-P. Soininen. Mappability estimate: A measure of the goodness of a processor-algorithm pair. In International Symposium on System-on-Chip Proceedings, pages 119–122, Tampere, Finland, November 2003.
U. Krishnaswamy and I. D. Scherson. A framework for computer performance evaluation using benchmark sets. IEEE Transactions on Computers, 49(12):1325–1338, December 2000.
M. Lazarescu, J. Bammi, E. Harcourt, L. Lavagno, and M. Lajolo. Compilation-based software performance estimation for system level design. In Proceedings of High Level Design Validation and Test Workshop, pages 167–172, November 2000.
C. Marcon, A. Borin, A. Susin, L. Carro, and F. Wagner. Time and energy efficient mapping of embedded applications onto nocs. In Proceedings of the Asia and South Pacific Design Automation Conference, pages 33–38, January 2005.
M. Oyamada, F. R. Wagner, M. Bonaciu, W. Cesario, and A. Jerraya. Software performance estimation in mpsoc design. In Asia and South Pacific Design Automation Conference, pages 38–43, January 2007.
J.-P. Soininen, J. Kreku, Y. Qu, and M. Forsel. Fast processor core selection for wlan modem using mappability estimation. In Proceedings of the 10th International Symposium on Hardware-Software Codesign (CODES), pages 61–66, Estes Park, Colorado, 2002.
J.-P. Soininen, J. Kreku, Y. Qu, and M. Forsell. Mappability estimation approach for processor architecture evaluation. In Proceedings of the 20th IEEE Norchip Conference, pages 171–176, 2002.
K. Suzuki and A. Sangiovanni-Vincentelli. Efficient software performance estimation methods for hardware/software codesign. In 33rd Design Automation Conference, pages 605–610, 1996.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Kreku, J., Tiensyrjä, K., Wieferink, A., Vanthournout, B. (2012). ASIP Exploration and Design. In: Soudris, D., Jantsch, A. (eds) Scalable Multi-core Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6778-7_4
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6778-7_4
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-6777-0
Online ISBN: 978-1-4419-6778-7
eBook Packages: EngineeringEngineering (R0)