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Extreme Statistics in Nanoscale Memory Design pp 137–177Cite as

Yield Estimation by Computing Probabilistic Hypervolumes

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Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

Parameter variations are inevitable in any IC process. Process steps such as oxidation, doping, molecular beam epitaxy, etc., are all fundamentally statistical in nature [1]. Design of functioning circuits and systems has traditionally relied heavily on the presumption that the law of large numbers [2] applies and that statistical averaging predominates over random variations – more precisely, that the statistical distributions of important process, geometrical, environmental, and electrical parameters cluster closely about their means. Unfortunately, with feature sizes having shrunk from 90 to 65 nm recently (with further scaling down to 45 and 32 nm predicted by the ITRS roadmap [3]), this assumption is no longer valid – in spite of efforts to control them [4, 5], large variations in process parameters are the norm today. This problem is most severe for circuits that try to use the minimum transistor size (e.g., memory circuits [6] for which chip area is of high priority). With transistors having become extremely small (e.g.: gates are only 10 molecules thick; minority dopants in the channel number in the 10s of atoms), small absolute variations in previous processes have become large relative ones. Lithography-related variability at nanoscales [5], which affect geometrical parameters such as effective length and width, further compound parameter variation problems.

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Notes

  1. 1.

    For the design centering problem, the parameters to be determined are normally physical parameters, such as transistor width W and length L; For the yield estimation problem, the parameters are “statistical” ones, such as threshold voltage V t and channel length variation ΔL.

  2. 2.

    This is the case when the boundary is defined by one performance constraint. The multiple-constraint case will be discussed in Sect. 6.3.1.

  3. 3.

    There are a few variations of this algorithm, but the basic structures are almost the same.

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Authors and Affiliations

  1. University of California, Berkeley, USA

    Chenjie Gu

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  1. Chenjie Gu
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  2. Jaijeet Roychowdhury
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Correspondence to Chenjie Gu .

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Editors and Affiliations

  1. T.J. Watson Research Center, IBM Corporation, Kitchawan Road Route 134 1101, Yorktown Heights, 10598, New York, USA

    Amith Singhee

  2. Department of Computer Science, University of Illinois at Urbana-Champai, N. Goodwin Ave 201, Urbana, 61801, Illinois, USA

    Rob A. Rutenbar

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Gu, C., Roychowdhury, J. (2010). Yield Estimation by Computing Probabilistic Hypervolumes. In: Singhee, A., Rutenbar, R. (eds) Extreme Statistics in Nanoscale Memory Design. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6606-3_6

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  • DOI: https://doi.org/10.1007/978-1-4419-6606-3_6

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