• Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny


This chapter provides a brief introduction into SystemVerilog Assertions (SVA). The main concepts are explained on specific examples. We explain the peculiarities of the assertion language and its application in the contemporary design flow. The chapter discusses assertion kinds, assertion reuse and tools for assertion library support. The chapter is concluded with a brief comparison between PSL and SVA.


Clock Cycle Finite State Machine Formal Verification High Level Model Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Scinece+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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