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Introduction

  • Eduard Cerny
  • Surrendra Dudani
  • John Havlicek
  • Dmitry Korchemny
Chapter

Abstract

This chapter provides a brief introduction into SystemVerilog Assertions (SVA). The main concepts are explained on specific examples. We explain the peculiarities of the assertion language and its application in the contemporary design flow. The chapter discusses assertion kinds, assertion reuse and tools for assertion library support. The chapter is concluded with a brief comparison between PSL and SVA.

Keywords

Clock Cycle Finite State Machine Formal Verification High Level Model Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 2.
    IEEE Standard Verilog Hardware Description Language (2001) IEEE Std 1364-2001, pp 1–856Google Scholar
  2. 4.
    IEEE Standard for Verilog Hardware Description Language (2006) IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), pp 1–560Google Scholar
  3. 5.
    IEEE Standard SystemC Language Reference Manual (2006) IEEE Std 1666-2005, pp 1–423Google Scholar
  4. 6.
    IEC Standard for Property Specification Language (PSL) (Adoption of IEEE Std 1850-2005) (2007) IEC 62531:2007 (E), pp 1–156Google Scholar
  5. 7.
    IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language (2009) IEEE STD 1800-2009, pp C1–1285Google Scholar
  6. 12.
    Ashar P, Dey S, Malik S (1995) Exploiting multicycle false paths in the performance optimization of sequential logic circuits. In: IEEE transactions on computer-aided design of integrated circuits and systems 14(9):1067–1075CrossRefGoogle Scholar
  7. 15.
    Bergeron J, Cerny E, Hunter A, Nightingale A (2006) Verification methodology manual for SystemVerilog. Springer, New YorkGoogle Scholar
  8. 16.
    Bernardo M, Cimatti A (2006) Formal methods for hardware verification: 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM … Lectures (Lecture Notes in Computer Science). Springer, New York, Secaucus, NJ, USAGoogle Scholar
  9. 21.
    Chadha R (2009) Static timing analysis for nanometer designs. SpringerGoogle Scholar
  10. 28.
    Emerson EA, Halpern JY (1982) Decision procedures and expressiveness in the temporal logic of branching time. In: STOC’82: Proceedings of the fourteenth annual ACM symposium on Theory of computing. ACM, New York, pp 169–180Google Scholar
  11. 33.
    Gulati K, Khatri SP (2010) Hardware acceleration of EDA algorithms. Custom ICs, FPGAs and GPUs. SpringerGoogle Scholar
  12. 37.
    Hennessy JL, Patterson DA (2006) Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann Publishers, San Francisco, CA, USAMATHGoogle Scholar
  13. 39.
    Kuehlmann A, van Eijk CAJ (2002) Combinational and sequential equivalence checking. Logic synthesis and verification, pp 343–372Google Scholar
  14. 42.
    Lamport L (2002) Specifying systems, the TLA+ language and tools for hardware and software engineers. Addison-WesleyGoogle Scholar
  15. 43.
    Malik S (2005) A case for runtime validation of hardware. In: Haifa verification conference. pp 30–42Google Scholar
  16. 45.
    Mukhopadhyay R, Panda SK, Dasgupta P, Gough J (2009) Instrumenting ams assertion verification on commercial platforms. ACM Trans Des Autom Electron Syst 14(2):1–47CrossRefGoogle Scholar
  17. 47.
    Parker RH (2004) Caution: clock crossing. a prescription for uncontaminated data across clock domains. Chip design magazineGoogle Scholar
  18. 48.
    Pellauer M, Lis M, Baltus D, Nikhil R (2005) Synthesis of synchronous assertions with guarded atomic actions. In: 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design. IEEE Computer Society, Washington, DC. pp 15–24Google Scholar
  19. 49.
    Reese RB, Thornton MA (2006) Introduction to logic synthesis using verilog HDL (synthesis lectures on digital circuits and systems). Morgan and ClaypoolGoogle Scholar
  20. 50.
    Rotithor H (2000) Postsilicon validation methodology for microprocessors. IEEE Des Test 17(4):77–88CrossRefGoogle Scholar
  21. 55.
    Sutherland S, Davidman S, Flake P (2006) SystemVerilog for Design. SpringerGoogle Scholar
  22. 56.
    Tabakov D, Vardi MY, Kamhi G, Singerman E (2008) A temporal language for systemc. In: FMCAD ’08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, IEEE, Piscataway, NJ, USA, pp 1–9Google Scholar

Copyright information

© Springer Scinece+Business Media, LLC 2010

Authors and Affiliations

  • Eduard Cerny
    • 1
  • Surrendra Dudani
    • 2
  • John Havlicek
    • 3
  • Dmitry Korchemny
    • 4
  1. 1.WorcesterUSA
  2. 2.NewtonUSA
  3. 3.AustinUSA
  4. 4.Kfar-SabaIsrael

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