Abstract
Unlike conventional digital CMOS circuits where there is no static power consumption (neglecting the leakage current), in source-coupled logic (SCL) topology each cell consumes a specifc amount of constant bias current. During each transition, this current is charging or discharging the load capacitance. Hence, more static bias current directly translates into faster transitions at the output nodes of an SCL circuit. When there is no transition at the input of an SCL gate, on the other hand, the static bias current of the gate is only used to preserve the output voltage levels on the desired values. Therefore, there is specifc amount of static power consumption even during static operating conditions which is not used for processing purpose. Regarding that, as the circuit activity rate or duty rate reduces, the power effciency of SCL topology degrades quickly. Under these conditions where the activity rate is low, CMOS circuits can over a better power compromise
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Tajalli, A., Leblebici, Y. (2010). Subthreshold Source-Coupled Logic Performance Analysis. In: Extreme Low-Power Mixed Signal IC Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6478-6_5
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DOI: https://doi.org/10.1007/978-1-4419-6478-6_5
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