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From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations

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Abstract

Hard real-time embedded systems are often designed as automatic control systems that can include both continuous and discrete parts. The functional specification of such systems is usually done in a conditioned data-flow formalism such as Simulink or Scade. These formalisms are either quasi-synchronous or synchronous, and they go beyond the classical data-flow model by introducing a form of conditional execution allowing the description of hierarchical execution modes. Specific real-time implementation approaches have been proposed for such formalisms, which exploit the hierarchical conditions to improve the generated code. We present one such approach which takes as input data-flow synchronous specifications and uses static scheduling heuristics to automatically produce efficient distributed real-time implementations. We explain how improving the analysis of the hierarchical conditions results in better implementations.

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Notes

  1. 1.

    Clocks can be easily extended to include cycle indices, which is of help when dealing with multi-periodic systems.

  2. 2.

    This does not contradict the single assignment rule because the dataflow functions F1 and G that produce ID cannot be both executed in a cycle.

  3. 3.

    Such a formalism can also represent coarser-grain allocation policies where allocation is done at some other hierarchy level.

  4. 4.

    The results of this chapter can be extended to the case where cycles can overlap by considering modulo scheduling techniques.

References

  1. Arditi, L., Boufaïed, H., Cavanié, A., Stehlé, V.: Coverage-directed generation of system-level test cases for the validation of a DSP system. In: FME 2001: Formal Methods for Increasing Software Productivity. Lecture Notes in Computer Science, vol. 2021. Springer, Berlin (2001)

    Google Scholar 

  2. Benveniste, A., Berry, G.: The synchronous approach to reactive and real-time systems. Proceedings of the IEEE 79(9), 1270–1282 (1991)

    Article  Google Scholar 

  3. Benveniste, A., Caspi, P., Edwards, S.A., Halbwachs, N., Guernic, P.L., de Simone, R.: The synchronous languages 12 years later. Proceedings of the IEEE 91(1), 64–83 (2003)

    Article  Google Scholar 

  4. Berry, G.: Real-time programming: general-purpose or special-purpose languages. In: G. Ritter (ed.) Information Processing 89, pp. 11–17. Elsevier, Amsterdam (1989)

    Google Scholar 

  5. Berry, G.: The constructive semantics of Pure Esterel. Esterel Technologies. Electronic version available at http://www.esterel-technologies.com (1999)

    Google Scholar 

  6. Berry, G., Gonthier, G.: The Esterel synchronous programming language: design, semantics, implementation. Science of Computer Programming 19(2), 87–152 (1992)

    Article  MATH  Google Scholar 

  7. Bouali, A.: XEVE, an Esterel verification environment. In: Proceedings of the Tenth International Conference on Computer Aided Verification (CAV’98). UBC, Vancouver, Canada. Lecture Notes in Computer Science, vol. 1427. Springer, Berlin (1998)

    Google Scholar 

  8. Bouali, A., Marmorat, J.P., de Simone, R., Toma, H.: Verifying synchronous reactive systems programmed in ESTEREL. In: Proceedings FTRTFT’96. Lecture Notes in Computer Science, vol. 1135, pp. 463–466. Springer, Berlin (1996)

    Google Scholar 

  9. Burns, A., Tindell, K., Wellings, A.: Effective analysis for engineering real-time fixed priority schedulers. IEEE Transactions on Software Engineering 21(5), 475–480 (1995)

    Article  Google Scholar 

  10. Caspi, P., Curic, A., Maignan, A., Sofronis, C., Tripakis, S., Niebert, P.: From Simulink to SCADE/Lustre to TTA: a layered approach for distributed embedded applications. In: Proceedings LCTES (2003)

    Google Scholar 

  11. Cohen, A., Duranton, M., Eisenbeis, C., Pagetti, C., Plateau, F., Pouzet, M.: N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems. In: ACM International Conference on Principles of Programming Languages (POPL’06). Charleston, SC, USA (2006)

    Google Scholar 

  12. Cucu, L., Pernet, N., Sorel, Y.: Periodic real-time scheduling: from deadline-based model to latency-based model. Annals of Operations Research 159(1), 41–51 (2008). http://www-rocq.inria.fr/syndex/publications/pubs/aor07/aor07.pdf

    Article  MathSciNet  MATH  Google Scholar 

  13. Danne, K., Platzner, M.: An EDF schedulability test for periodic tasks on reconfigurable hardware devices. In: Proceedings of the Conference on Language, Compilers, and Tool Support for Embedded Systems, ACM SIGPLAN/SIGBED. Ottawa, Canada (2006)

    Google Scholar 

  14. Dennis, J.: First version of a dataflow procedure language. In: Lecture Notes in Computer Science, vol. 19, pp. 362–376. Springer, Berlin (1974)

    Google Scholar 

  15. Eles, P., Kuchcinski, K., Peng, Z., Pop, P., Doboli, A.: Scheduling of conditional process graphs for the synthesis of embedded systems. In: Proceedings of DATE. Paris, France (1998)

    Google Scholar 

  16. Gao, M., Jiang, J.H., Jiang, Y., Li, Y., Sinha, S., Brayton, R.: MVSIS. In: Proceedings of the International Workshop on Logic Synthesis (IWLS’01). Tahoe City (2001)

    Google Scholar 

  17. Grandpierre, T., Sorel, Y.: From algorithm and architecture specification to automatic generation of distributed real-time executives. In: Proceedings MEMOCODE (2003)

    Google Scholar 

  18. Gu, Z., He, X., Yuan, M.: Optimization of static task and bus access schedules for time-triggered distributed embedded systems with model-checking. In: Proceedings DAC (2007)

    Google Scholar 

  19. Guernic, P.L., Talpin, J.P., Lann, J.C.L.: Polychrony for system design. Journal for Circuits, Systems and Computers 12(3), 261–303 (2003). Special Issue on Application Specific Hardware Design

    Article  Google Scholar 

  20. Halbwachs, N.: Synchronous programming of reactive systems. In: Computer Aided Verification (CAV’98), pp. 1–16 (1998). citeseer.ist.psu.edu/article/halbwachs98synchronous.html

    Chapter  Google Scholar 

  21. Halbwachs, N., Caspi, P., Raymond, P., Pilaud, D.: The synchronous dataflow programming language Lustre. Proceedings of the IEEE 79(9), 1305–1320 (1991)

    Article  Google Scholar 

  22. Kermia, O., Cucu, L., Sorel, Y.: Non-preemptive multiprocessor static scheduling for systems with precedence and strict periodicity constraints. In: Proceedings of the 10th International Workshop on Project Management and Scheduling, PMS’06. Posnan, Poland (2006). http://www-rocq.inria.fr/syndex/publications/pubs/pms06/pms06.pdf

    Google Scholar 

  23. Kermia, O., Sorel, Y.: Load balancing and efficient memory usage for homogeneous distributed real-time embedded systems. In: Proceedings of the 4th International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, SRMPDS’08. Portland, Oregon, USA (2008). http://www-rocq.inria.fr/syndex/publications/pubs/srmpds08/srmpds08.pdf

    Google Scholar 

  24. Kermia, O., Sorel, Y.: Schedulability analysis for non-preemptive tasks under strict periodicity constraints. In: Proceedings of 14th International Conference on Real-Time Computing Systems and Applications, RTCSA’08. Kaohsiung, Taiwan (2008). http://www-rocq.inria.fr/syndex/publications/pubs/rtcsa08/rtcsa08.pdf

    Google Scholar 

  25. Kountouris, A., Wolinski, C.: Efficient scheduling of conditional behaviors for high-level synthesis. ACM Transactions on Design Automation of Electronic Systems 7(3), 380–412 (2002)

    Article  Google Scholar 

  26. Leung, J., Whitehead, J.: On the complexity of fixed-priority scheduling of periodic real-time tasks. Performance Evaluation 2(4), 237–250 (1982)

    Article  MathSciNet  MATH  Google Scholar 

  27. Liu, C., Layland, J.: Scheduling algorithms for multiprogramming in a hard real-time environment. Journal of ACM 14(2), 46–61 (1973)

    Article  MathSciNet  Google Scholar 

  28. Lopez, J.M., Garcia, M., Diaz, J.L., Garcia, D.F.: Worst-case utilization bound for EDF scheduling on real-time multiprocessor system. In: Proceedings of 19th Euromicro Conference on Real-Time Systems, ECRTS’00. Stockholm, Sweden (2000)

    Google Scholar 

  29. Obermeisser, R.: Event-Triggered and Time-Triggered Control Paradigms. Springer, Berlin (2005)

    Google Scholar 

  30. Potop-Butucaru, D., Caillaud, B., Benveniste, A.: Concurrency in synchronous systems. Formal Methods in System Design 28(2), 111–130 (2006)

    Article  MATH  Google Scholar 

  31. Potop-Butucaru, D., de Simone, R., Sorel, Y., Talpin, J.P.: Clock-driven distributed real-time implementation of endochronous synchronous programs. In: Proceedings EMSOFT’09. Grenoble, France (2009)

    Google Scholar 

  32. The Scade tool page: http//www.esterel-technologies.com/products/scade-suite/

  33. Schneider, K.: Proving the equivalence of microstep and macrostep semantics. In: 15th International Conference on Theorem Proving in Higher Order Logics (2002)

    Google Scholar 

  34. Sentovich, E., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Brayton, R., Sagiovanni-Vincentelli, A.: SIS: a system for sequential circuit synthesis. Memorandum UCB/ERL M92/41, UCB, ERL (1992)

    Google Scholar 

  35. Sentovich, E., Toma, H., Berry, G.: Latch optimization in circuits generated from high-level descriptions. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD’96) (1996)

    Google Scholar 

  36. Shiple, T., Berry, G., Touati, H.: Constructive analysis of cyclic circuits. In: Proceedings of the International Design and Testing Conference (ITDC). Paris (1996)

    Google Scholar 

  37. de Simone, R., Ressouche, A.: Compositional semantics of Esterel and verification by compositional reductions. In: Proceedings CAV’94. Lecture Notes in Computer Science, vol. 818. Springer, Berlin (1994)

    Google Scholar 

  38. The Simulink tool page: http://www.mathworks.com/products/simulink/

  39. Singh, M., Theobald, M.: Generalized latency-insensitive systems for single-clock and multi-clock architectures. In: Proceedings DATE (2004)

    Google Scholar 

  40. Susini, J.F., Hazard, L., Boussinot, F.: Distributed reactive machines. In: Proceedings RTCSA (1998)

    Google Scholar 

  41. Touati, H., Berry, G.: Optimized controller synthesis using Esterel. In: Proceedings of the International Workshop on Logic Synthesis (IWLS’93). Lake Tahoe (1993)

    Google Scholar 

  42. Zheng, W., Chong, J., Pinello, C., Kanajan, S., Sangiovanni-Vincentelli, A.: Extensible and scalable time triggered scheduling. In: Proceedings ACSD (2005)

    Google Scholar 

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Authors and Affiliations

  1. INRIA, Centre de Recherche de Paris-Rocquencourt, Le Chesnay Cedex, France

    Dumitru Potop-Butucaru & Yves Sorel

  2. INRIA, Centre de Recherche de Sophia-Antipolis, Sophia Antipolis Cedex, France

    Robert de Simone

Authors
  1. Dumitru Potop-Butucaru
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  2. Robert de Simone
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  3. Yves Sorel
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Correspondence to Dumitru Potop-Butucaru .

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Editors and Affiliations

  1. Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Whittemore Hall 302, Blacksburg, 24061, USA

    Sandeep K. Shukla

  2. INRIA Rennes-Bretagne Atlantique, Rennes CX, 35042, France

    Jean-Pierre Talpin

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Potop-Butucaru, D., de Simone, R., Sorel, Y. (2010). From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations. In: Shukla, S., Talpin, JP. (eds) Synthesis of Embedded Software. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6400-7_8

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  • DOI: https://doi.org/10.1007/978-1-4419-6400-7_8

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