The Time Model of Logical Clocks Available in the OMG MARTE Profile



Multiform logical time, introduced and made popular through its central role in Synchronous Language theory, is already present in many formalisms pertaining to embedded system design, although usually in a hidden fashion. Logical time considers time bases that can be generated from any sort of sequences of events, not necessarily equally spaced in physical time. Our main goal here is to capture some of the essence of multiform logical time, and encapsulate it into a dedicated syntax (CCSL, Clock Constraint Specification Language, part of the UML profile for MARTE). CCSL provides ways to express loose or strict constraints between distinct logical clocks. Solving such clock constraints amounts to relating clocks to a common reference one, which then can be thought of as closer to physical. We motivate the role of MARTE Time Model and CCSL by using them to explain and formally characterize important semantic features of East-ADL/AUTOSAR, AADL, and Ptolemy’s SDC models.


Unify Modeling Language Unify Modeling Language Model Schedulability Analysis Object Node Clock Constraint 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer US 2010

Authors and Affiliations

  1. 1.Laboratoire I3S, UMR 6070 CNRS, Université Nice-Sophia Antipolis, INRIA Sophia Antipolis MéditerranéeSophia AntipolisFrance

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