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Compilation of Polychronous Data Flow Equations

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Synthesis of Embedded Software

Abstract

High-level embedded system design has gained prominence in the face of rising technological complexity, increasing performance requirements and shortening time to market demands for electronic equipments. Today, the installed base of intellectual property (IP) further stresses the requirements for adapting existing components with new services within complex integrated architectures, calling for appropriate mathematical models and methodological approaches to that purpose.

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Author information

Authors and Affiliations

  1. CNRS/IRISA, Campus de Beaulieu, Rennes, France

    Loïc Besnard

  2. INRIA, Centre de Recherche de Rennes, Campus de Beaulieu, Rennes, France

    Thierry Gautier, Paul Le Guernic & Jean-Pierre Talpin

Authors
  1. Loïc Besnard
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  2. Thierry Gautier
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  3. Paul Le Guernic
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  4. Jean-Pierre Talpin
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Corresponding author

Correspondence to Thierry Gautier .

Editor information

Editors and Affiliations

  1. Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Whittemore Hall 302, Blacksburg, 24061, USA

    Sandeep K. Shukla

  2. INRIA Rennes-Bretagne Atlantique, Rennes CX, 35042, France

    Jean-Pierre Talpin

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Besnard, L., Gautier, T., Le Guernic, P., Talpin, JP. (2010). Compilation of Polychronous Data Flow Equations. In: Shukla, S., Talpin, JP. (eds) Synthesis of Embedded Software. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6400-7_1

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  • DOI: https://doi.org/10.1007/978-1-4419-6400-7_1

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-6399-4

  • Online ISBN: 978-1-4419-6400-7

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