Abstract
An instruction set simulator is an important tool for system architects and for software developers. However, when implementing a simulator, there are many choices which can be made and that have an effect on the speed and the accuracy of the simulation. They are especially relevant to DSP simulation. This chapter explains the different strategies for implementing a simulator.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
August, D., Chang, J., Girbal, S., Gracia-Perez, D., Mouchard, G., Penry, D.A., Temam, O., Vachharajani, N.: An open simulation environment and library for complex architecture design and collaborative development, IEEE Computer Architecture Letters, 6(2):45–48 (2007)
Austin, T., Larson, E., Ernst, D.: SimpleScalar: An infrastructure for computer system modeling. Computer, 35(2):59–67, (2002)
Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros.,E.: The ArchC architecture description language and tools, Int. J. Parallel Program., 33(5):453–484, (2005)
Bartholomeu, M., Azevedo, R., Rigo, S., Araujo, G.: Optimizations for compiled simulation using instruction type information, Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), pages 74–81, (2004)
Bell, J.R.: Threaded code, Commun. ACM, 16(6):370–372 (1973)
Brandner, F., Fellnhofer, A., Krall, A., Riegler, D.: Fast and accurate simulation using the LLVM compiler framework, RAPIDO ’09: 1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, (2009)
Burtscher, M., Ganusov, I.: Automatic synthesis of high-speed processor simulators, MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, pages 55–66, (2004)
Bermudo, N., Horspool, R.N., Krall, A.: Control flow graph reconstruction for reverse compilation of assembly language programs with delayed instructions, SCAM’05: Proceedings of the Fifth InternationalWorkshop on Source Code Analysis andManipulation, pages 107–116, (2005)
Brandner, F.: Precise simulation of interrupts using a rollback mechanism, SCOPES ’09: Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, pages 71–80, (2009)
Cofer, R.C., Harding, B.: Rapid System Prototyping with FPGAs: Accelerating the Design Process, Newnes, (2005)
Chung, E.S., Hoe, J.C., Falsafi, B.: ProtoFlex: Co-simulation for component-wise FPGA emulator development, WARFP ’06: In Proceedings of the 2nd Workshop on Architecture Research using FPGA Platforms, (2006)
Cmelik, B., Keppel, D.: Shade: A fast instruction-set simulator for execution profiling, SIGMETRICS ’94: Proceedings of the 1994 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pages 128–137, (1994)
Chung, E.S., Nurvitadhi, E., Hoe, J.C., Falsafi, B., Mai, K.: A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA ’08: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, pages 77–86, (2008)
Chung, E.S., Papamichael, M.K., Nurvitadhi, E., Hoe, J.C., Mai, K., Falsafi, B.: ProtoFlex: Towards scalable, full-system multiprocessor simulations using FPGAs. ACM Transactions on Reconfigurable Technology and Systems, 2(2):1–32, (2009)
Chiou, D., Sunwoo, D., Kim, J., Patil, N., Reinhart, W.H., Johnson, D.E., Xu, Z.: The FAST methodology for high-speed SoC/computer simulation, ICCAD ’07: Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design, pages 295–302, (2007)
Chiou, D., Sunwoo, D., Kim, J., Patil, N., Reinhart, W.H., Johnson, D.E., Keefe, J., Angepat, H.: FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators, MICRO ’07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pages 249–261, (2007)
Chiou, D., Sanjeliwala, H., Sunwoo, D., Xu, J.Z., Patil, N.: FPGA-based fast, cycle-accurate, full-system simulators, WARFP’06: Proceedings of the second Workshop on Architecture Research using FPGA Platforms, (2006)
Dehnert, J.C., Grant, B.K, Banning, J.P., Johnson, R., Kistler, T., Klaiber, A.,Mattson, J.: The Transmeta Code MorphingTM software: Using speculation, recovery, and adaptive retranslation to address real-life challenges, CGO ’03: Proceedings of the International Symposium on Code Generation and Optimization, pages 15–24, (2003)
Ebcio˘glu, K.,Altman, E.R.: DAISY: Dynamic compilation for 100% architectural compatibility, ISCA ’97: Proceedings of the 24th International Symposium on Computer Architecture, pages 26–37, (1997)
Emer, J., Ahuja, P., Borch, E., Klauser, A., Luk, C.-K., Manne, S., Mukherjee, S.S., Patil, H., Wallace, S., Binkert, N., Espasa, R., Juan, T.: Asim: A performance model framework, Computer, 35(2):68–76, (2002)
Ebcio˘glu, K., Altman, E.R., Gschwind, M., Sathaye, S.: Optimizations and oracle parallelism with dynamic translation, MICRO 32: Proceedings of the 32nd annual ACM/IEEE International Symposium on Microarchitecture, pages 284–295, (1999)
Ebcio˘glu, K., Altman, E., Gschwind, M., Sathaye, S.: Dynamic binary translation and optimization, IEEE Transactions on Computers, 50(6):529–548, (2001)
Errico, J.D., Qin, W.: Constructing portable compiled instruction-set simulators - an ADLdriven approach, DATE ’06: Proceedings of the Conference on Design, Automation and Test in Europe, pages 112–117, (2006)
Farfeleder, S., Krall, A., Horspool, R.N.: Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures, EUROMICRO Journal of Systems Architecture, 53(8):501–510, (2007)
Fytraki, S., Pnevmatikatos, D.: ReSim, a trace-driven, reconfigurable ILP processor simulator, DATE ’09: Proceedings of Design, Automation and Test in Europe 2009, (2009)
Fauth, A., Van Praet, J., Freericks, M.: Describing instruction set processors using nML, EDTC ’95: Proceedings of the 1995 European Conference on Design and Test, pages 503–507, (1995)
Gschwind, M., Altman, E.: Optimization and precise exceptions in dynamic compilation, ACM SIGARCH Computer Architecture News, 29(1):66–74, (2001)
Gschwind, M., Altman, E.R., Sathaye, S., Ledak, P., Appenzeller, D.: Dynamic and transparent binary translation, Computer, 33(3):54–59, (2000)
Gao, L., Kraemer, S., Leupers, R., Ascheid, G., Meyr, H.. A fast and generic hybrid simulation approach using C virtual machine, CASES ’07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 3–12, (2007)
Goossens, G., Lanneer, D., Geurts, W., Van Praet, J.: Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite, International Symposium on Systemon-Chip, pages 1–4, (2006)
Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: A language for architecture exploration through compiler/simulator retargetability, DATE ’99: Proceedings of the Conference on Design, Automation and Test in Europe, pages 485–490, (1999)
Ienne, P., Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications (Systems on Silicon), Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, (2006)
Jones, D., Topham, N.P.: High speed CPU simulation using LTU dynamic binary translation. In HiPEAC’09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, pages 50–64, (2009)
Krall, A., Farfeleder, S., Horspool, R.N.: Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures, SAMOS ’05: Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, LNCS 3553, pages 222–231, (2005)
Kudlugi,M., Hassoun, S., Selvidge, C., Pryor, D.: A transaction-based unified simulation/emulation architecture for functional verification. DAC ’01: Proceedings of the 38th Conference on Design Automation, pages 623–628, (2001)
Klint, P.: Interpretation techniques, Software: Practice and Experience, 11(9):963– 973, (1981)
Larus, J. Assemblers, linkers and the SPIM simulator, in Patterson, D.A., Hennessy, J.L., editors, Computer Organization and Design: The Hardware/software Interface, Morgan Kaufmann, (2005)
Mills, C., Ahalt, S.C., Fowler, J.: Compiled instruction set simulation, Software: Practice and Experience, 21(8):877–889, (1991)
Magnusson, P.S.. Efficient instruction cache simulation and execution profiling with a threaded-code interpreter, WSC ’97: Proceedings of the 29th Conference on Winter Simulation, pages 1093–1100, (1997)
May, C.: Mimic: a fast System/370 simulator, Symposium on Interpreters and Interpretive Techniques, pages 1–13, (1987)
Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hållberg, G., Högberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: A full system simulation platform, Computer, 35(2):50–58, (2002)
Mishra, P. and Dutt, N.: Processor Description Languages, Volume 1, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, (2008)
Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H., Hoffmann, A.: A universal technique for fast and flexible instruction-set architecture simulation, DAC ’02: Proceedings of the 39th Conference on Design Automation, pages 22–27, (2002)
Nakamura, Y., Hosokawa, K.. Fast FPGA-emulation-based simulation environment for custom processors, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A(12):3464–3470, (2006)
Nakamura, Y., Hosokawa, K., Kuroda, K., Yoshikawa, K., Yoshimura, T.: A fast hardware/-software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication, DAC ’04: Proceedings of the 41st annual Conference on Design Automation, pages 299–304, (2004)
Pees, S., Hoffmann, A., Meyr, H.: Retargetable compiled simulation of embedded processors using a machine description language, ACM Transactions on Design Automation of Electronic Systems, 5(4):815–834, (2000)
Proebsting, T.A.: Optimizing an ANSI C interpreter with superoperators, POPL ’95: Proceedings of the 22nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pages 322–332, (1995)
Pellauer, M., Vijayaraghavan, M., Adler, M., Arvind, Emer, J.: Quick performance models quickly: Closely-coupled partitioned simulation on FPGAs, ISPASS ’08: IEEE International Symposium on Performance Analysis of Systems and Software, pages 1–10, (2008)
Pellauer, M., Vijayaraghavan, M., Adler, M., Arvind, Emer, J.: A-Ports: An efficient abstraction for cycle-accurate performance models on FPGAs, FPGA ’08: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, pages 87–96, (2008)
Roeven, H., Coninx, J., Ade, M.: CoolFlux DSP: The embedded ultra low power Cprogrammable DSP core, GSPx’04: International Signal Processing Conference, pages 1–7, (2004)
Reshadi, M., Dutt, N.: Generic pipelined processor modeling and high performance cycleaccurate simulator generation, DATE ’05: Proceedings of the Conference on Design, Automation and Test in Europe, pages 786–791, (2005)
Reshadi, M., Dutt, N., Mishra, P.: A retargetable framework for instruction-set architecture simulation, ACM Transactions on Embedded Computing Systems, 5(2):431–452, (2006)
Rosenblum, M., Herrod, S.A.,Witchel, E., Gupta, A.: Complete computer system simulation: The SimOS approach, IEEE Parallel & Distributed Technology, 3(4):34–43, (1995)
Reshadi, M., Mishra, P., Dutt, N.: Instruction set compiled simulation: A technique for fast and flexible instruction set simulation, Proceedings of the 40th Conference on Design Automation, pages 758–763, (2003)
Reshadi, M., Mishra, P., Dutt, N.: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation, ACM Transactions on Embedded Computing Systems, 8(3):1–27, (2009)
Schnerr, J., Bringmann, O., Rosenstiel, W.: Cycle accurate binary translation for simulation acceleration in rapid prototyping of SoCs, DATE ’05: Proceedings of the Conference on Design, Automation and Test in Europe, pages 792–797, (2005)
Sites, R.L., Chernoff, A., Kirk, M.B., Marks, M.P., Robinson, S.G.: Binary translation, Communications of the ACM, 36(2):69–81, (1993)
Schnerr, J., Haug, G., Rosenstiel, W.: Instruction set emulation for rapid prototyping of SoCs, DATE ’03: Proceedings of the Conference on Design, Automation and Test in Europe, pages 562–567, (2003)
Sathaye, S., Ledak, P., Leblanc, J., Kosonocky, S., Gschwind, M., Fritts, J., Bright, A., Altman, E., Agricola, C.: BOA: Targeting multi-gigahertz with binary translation, Proceedings of the 1999 Workshop on Binary Translation, pages 2–11, (1999)
Suh, T., Lee, H.-H.S., Lu, S.-L., Shen, J.: Initial observations of hardware/software cosimulation using FPGA in architectural research, WARFP’06: In Proceedings of the 2nd Workshop on Architecture Research using FPGA Platforms, (2006)
Smith, E., Nair, R.: Virtual Machines, Morgan Kaufman, (2005)
Open SystemC Initiative. http://www.systemc.org/home.
Vachharajani, M., Vachharajani, N., August, D.I.: The Liberty Structural Specification Language: A high-level modeling language for component reuse, PLDI ’04: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation, pages 195–206, (2004)
Vachharajani, M., Vachharajani, N., Penry, D.A., Blome, J.A., Malik, S., and August, D.I.: The Liberty Simulation Environment: A deliberate approach to high-level system modeling, ACM Transactions on Computer Systems, 24(3):211–249, (2006)
Witchel, E., Rosenblum, M.: Embra: Fast and flexible machine simulation, SIGMETRICS ’96: Proceedings of the 1996 ACMSIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pages 68–79, (1996)
Yi, J.J., Lilja, D.J.: Simulation of computer architectures: Simulators, benchmarks, methodologies, and recommendations, IEEE Transactions on Computers, 55(3):268–280, (2006)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Brandner, F., Horspool, N., Krall, A. (2010). DSP Instruction Set Simulation. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6345-1_24
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6345-1_24
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-6344-4
Online ISBN: 978-1-4419-6345-1
eBook Packages: EngineeringEngineering (R0)