Abstract
Modern systems consist of a hierarchy of memory arrays made of different storage elements such as SRAM, DRAM, FLASH, etc. The organization of a memory array significantly impacts its delay, power, bandwidth, and area parameters which in turn impacts overall system performance and cost. When evaluating a new architecture or exploring new memory designs, it is crucial to get an early estimate of memory access time and power for given input parameters. For studies related to memory hierarchy design, it is also necessary to optimize memory arrays so that they meet specific delay, area, and power constraints. This chapter presents an integrated analytical tool called CACTI that models power, delay, area, and cycle time (bandwidth) of all the components in a modern memory system. As all parameters are calculated based on the same technology and circuit parameters, they are mutually consistent, and the analytical models employed in CACTI have been verified to be within 12% of high fidelity SPICE models. This chapter explains the fundamental building blocks of memory arrays along with their analytical delay, power, and area models and details tradeoffs that exist when designing them.
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Acknowledgments
The authors would like to thank all the researchers that have contributed to CACTI over the past 15 years, including Steve Wilton, Glenn Reinman, Premkishore Shivakumar, David Tarjan, and Shyamkumar Thoziyoor.
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Muralimanohar, N., Ahn, J.H., Jouppi, N.P. (2010). Memory Modeling with CACTI. In: Leupers, R., Temam, O. (eds) Processor and System-on-Chip Simulation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6175-4_14
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DOI: https://doi.org/10.1007/978-1-4419-6175-4_14
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