Abstract
The on-chip bus is the backbone of any SoC, and it is a means to efficiently connect various components including processors, memory, and peripherals. The challenges for an on-chip bus are not minor: it has to accommodate a wide range of communication needs with a single, unified architecture. In this chapter we review the key characteristics of the on-chip bus, using several existing on-chip bus standards as examples: ARM/AMBA, IBM/Coreconnect, and Wishbone. We also look at some of the long-term challenges for on-chip interconnect, and how this will affect the design of hardware–software interfaces.
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Schaumont, P.R. (2010). On-Chip Busses. In: A Practical Introduction to Hardware/Software Codesign. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6000-9_8
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DOI: https://doi.org/10.1007/978-1-4419-6000-9_8
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Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5999-7
Online ISBN: 978-1-4419-6000-9
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