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Flip-Chip Interconnections: Past, Present, and Future

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Advanced Flip Chip Packaging

Abstract

Flip-chip interconnection technologies have been extensively used in many microelectronic applications for high performance systems as well as consumer electronics in recent years. There are several types of flip-chip interconnects being used today in the industry, which include high-Pb solder bumps joined to a ceramic substrate, high-Pb bumps on chip joined to eutectic PbSn on a laminate substrate, all eutectic PbSn bumps, Pb-free bumps, Cu pillar bumps, and Au-stud bumps. Steady improvements have been made in high performance packages, such as having interconnects greater than 10,000 I/O’s with a pitch less than 200 μm, migrating from ceramic to low-cost organic substrates, replacing high-Pb with Pb-free interconnects, and others. Fundamental reliability issues, especially with the Pb-free solder bumps, remain to be solved. As the expiration of European Union (EU) Reduction of Hazardous Substance (RoHS) exemption approaches soon, Pb-containing solder bumps for flip-chip interconnects are expected to be phased out in a few years. However, the recent introduction of fragile low-k, or very fragile ultra low-k interlayer dielectrics (ILD) into the back-end interconnect architectures in the advanced semiconductor devices has imposed serious technical challenges in integrating Pb-free technologies for high-performance systems. How to control the cracking of low-k ILD layers during chip joining has become an urgent issue to be resolved together by the semiconductor and packaging industries. Another reliability challenge associated with the implementation of Pb-free solder in flip-chip packages is the poor electromigration (EM) performance of Sn-rich solders. This is mainly due to the highly anisotropic crystal structure of Sn, causing the fast solute diffusion along its c-axis, combined with the aggressive interfacial reactions with under-bump metallurgy (UBM) and laminate pads.

In this chapter, the recent progress of flip-chip assembly processes is presented with ceramic substrates and organic laminates, including the new bumping technologies such as C4NP and Cu pillar bumping. In addition, various reliability challenges of Pb-free, flip-chip applications are extensively discussed along with possible solutions for specific applications.

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Authors and Affiliations

  1. IBM Research Div, Yorktown Heights, NY, USA

    Sung-Kwon Kang & Da-Yuan Shih

  2. IBM Systems & Tech Group, Hopewell Junction, NY, USA

    William E. Bernier

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  1. Sung-Kwon Kang
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  2. Da-Yuan Shih
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  3. William E. Bernier
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Correspondence to Sung-Kwon Kang .

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    Yi-Shao Lai

  3. , Department of Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong, SAR, NT, China, People's Republic

    C.P. Wong

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Kang, SK., Shih, DY., Bernier, W.E. (2013). Flip-Chip Interconnections: Past, Present, and Future. In: Tong, HM., Lai, YS., Wong, C. (eds) Advanced Flip Chip Packaging. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-5768-9_4

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