Skip to main content
SpringerLink
Log in

Properties and Trade-Offs of Compound Semiconductor MOSFETs

  • Chapter
  • First Online:
Fundamentals of III-V Semiconductor MOSFETs

Abstract

In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials are required. A channel material with high mobility and therefore high injection velocity can increase ON current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs. However, looking into future high mobility III-V materials can offer several advantages over even very highly strained Si.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R. Chau, “Benchmarking nanotechnology for high performance and low-power logic transistor applications,” IEEE Transactions on Nanotechnology, vol. 4, pp. 153–8, 2005.

    Article  Google Scholar 

  2. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick, and R. Chau, “High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stack” in Technical Digest—International Electron Devices Meeting, pp. 653–6, 2003.

    Google Scholar 

  3. T. Tezuka, N. Sugiyama, T. Mizuno, and S. Takagi, “Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels,” IEEE Transactions on Electron Devices, vol. 50, pp. 1328–33, 2003.

    Article  Google Scholar 

  4. H. Shang, K.-L. Lee, P. Kozlowski, C. D. Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Epitaxial silicon and germanium on buried insulator heterostructures and devices,” Applied Physics Letters, vol. 83, pp. 5443–5, 2003.

    Article  Google Scholar 

  5. H. Shang, J. O. Cho, X. Wang, P. M. Mooney, K. Lee, J. Rim, K. Ott, K. Chan, K. Guarinin, and M. Ieong, “Channel design and mobility enhancement in strained germanium buried channel MOSFETs” in Digest of Technical Papers—Symposium on VLSI Technology, pp. 204–5, 2004.

    Google Scholar 

  6. A. Ritenour, S. Yu, M. L. Lee, Z. Lu, W. Bai, A. Pitera, E. Fitzgerald, D. Kwong, and D. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode” in Technical Digest—International Electron Devices Meeting, pp. 433–6, 2003.

    Google Scholar 

  7. M. Lee, E. Fitzgerald, M. Bulsara, C. A. Currie, and A. Lochtefeld, “Strained Si, SiGe and Ge channels for high mobility metal oxide semiconductor field effect transistors,” Journal of Applied Physics, vol. 97, pp. 11101-1-27, 2005.

    Article  Google Scholar 

  8. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. Saraswat, “Low defect ultrathin fully strained Ge MOSFET on relaxed Si with high mobility and low Band-To-Band-Tunneling (BTBT)” in Digest of Technical Papers—Symposium on VLSI Technology, pp. 82–3, 2005.

    Google Scholar 

  9. T. Krishnamohan, C. Jungemann, and K. C. Saraswat, “A novel, very high performance, sub-20 nm depletion-mode double-gate (DMDG)” in Technical Digest—International Electron Devices Meeting, pp. 687–90, 2003.

    Google Scholar 

  10. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, and K. C. Saraswat, “High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: Experiments,” IEEE Transactions on Electron Devices, vol. 53, pp. 990–9, 2006.

    Article  Google Scholar 

  11. S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. J. Phillips, D. Wallis, P. Wilding, and R. Chau, “85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications” in Technical Digest—International Electron Devices Meeting, pp. 763–6, 2005.

    Google Scholar 

  12. D.-H. Kim, J. D. Alamo, J.-H. Lee, and K.-S. Seo, “Logic suitability of 50-nm In0.7Ga0.3AsHEMTs for Beyond-CMOS applications,” IEEE Transactions on Electron Devices, vol. 54, pp. 2606–13, 2007.

    Article  Google Scholar 

  13. M. L. Cohen and T. K. Bergstresser, “Band structures and pseudopotential form factors for fourteen semiconductors of the diamond and zinc-blende structures,” Physical Review, vol. 141, pp. 789, 1966.

    Article  Google Scholar 

  14. J. R. Chelikowsky and M. L. Cohen, “Nonlocal pseudopotential calculations for the electronic structure of eleven diamond and zinc-blende semiconductors,” Physical Review B, vol. 14, pp. 556, 1976.

    Article  Google Scholar 

  15. J. P. Walter and M. L. Cohen, “Calculated and measured reflectivity of ZnTe and ZnSe,” Physical Review B, vol. 1, pp. 2661, 1970.

    Article  Google Scholar 

  16. G. Weisz, “Band structure and fermi surface of white tin,” Physical Review, vol. 149, pp. 504, 1966.

    Article  Google Scholar 

  17. L.-W. Wang, J. Kim, and A. Zunger, “Electronic structures of [110]-faceted self-assembled pyramidal InAs/GaAs quantum dots,” Physical Review B, vol. 59, pp. 5679, 1999.

    Google Scholar 

  18. O. H. Nielsen and R. M. Martin, “Stresses in semiconductors: Ab initio calculations on Si, Ge, and GaAs,” Physical Review B, vol. 32, pp. 3792, 1985.

    Article  Google Scholar 

  19. E. O. Kane, “Zener tunneling in semiconductors,” Journal of Physics and Chemistry of Solids, vol. 12, pp. 181–8, 1959.

    Article  Google Scholar 

  20. D. Kim, T. Krishnamohan, Y. Nishi, and K. C. Saraswat, “Band to band tunneling limited off state current in ultra-thin body double gate FETs with high mobility materials: III-V, Ge and strained Si/Ge,” presented at IEEE SISPAD, Monterey, CA, 2006.

    Google Scholar 

  21. D. Kim, “Theoretical performance evaluations of NMOS double gate FETs with high mobility materials: Strained III-V, Ge and Si,” in Electrical Engineering, Ph. D. Dissertation (to be published). Stanford, Stanford University, 2009.

    Google Scholar 

  22. A. Rahman, M. S. Lundstrom, and A. W. Ghosh, “Generalized effective-mass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers,” Journal of Applied Physics, vol. 97, pp. 1–12, 2005.

    Article  Google Scholar 

  23. G. Bastard, “Theoretical investigations of superlattice band structure in the envelope-function approximation,” Physical Review B, vol. 25, pp. 7584, 1982.

    Article  Google Scholar 

  24. R. Landuer, “Electrical resistance of disordered one-dimensional Lattices,” Philosophical Magazine, vol. 21, pp. 863, 1970.

    Article  Google Scholar 

  25. M. V. Fischetti and S. E. Laux, “Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures–II: Submicrometer MOSFET's,” IEEE Transactions on Electron Devices, vol. 38, pp. 650–60, 1991.

    Article  Google Scholar 

  26. A. Asenov, K. Kalna, I. Thayne, and R. J. W. Hill, “Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications,” Microelectronic Engineering, vol. 84, pp. 2398–403, 2007.

    Article  Google Scholar 

  27. M. D. Michielis, D. Esseni, and F. Driussi, “Analytical models for the insight into the use of alternative channel materials in ballistic nano-MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, pp. 115–23, 2007.

    Article  Google Scholar 

  28. S. E. Laux, “A simulation study of the switching times of 22- and 17-nm gate-length SOI nFETs on high mobility substrates and Si,” IEEE Transactions on Electron Devices, vol. 54, pp. 2304–20, 2007.

    Article  Google Scholar 

  29. A. Pethe, T. Krishnamohan, D. Kim, S. Oh, and H.-S. P. Wong, “Investigation of the performance limits of III-V double-gate n-MOSFETs” in Technical Digest—International Electron Devices Meeting, pp. 605–8, 2005.

    Google Scholar 

  30. D. Kim, T. Krishnamohan, L. Smith, H.-S. P. Wong, and K. C. Saraswat, “Band to band tunneling study in high mobility materials: III-V, Si, Ge and strained SiGe,” in 2007 65th DRC Device Research Conference. South Bend, IN, pp. 57–8, 2007.

    Google Scholar 

  31. D. Kim, T. Krishnamohan, and K. C. Saraswat, “Performance evaluation of III-V double-gate n-MOSFETs” presented at 2008 Annual Device Research Conference (DRC), Santa Barbara, CA, 2008.

    Google Scholar 

  32. D. Kim, T. Krishnamohan, and K. C. Saraswat, “Performance evaluation of 15 nm gate length double-gate n-MOSFETs with high mobility channels: IIIV, Ge and Si,” ECS Transactions, vol. 16, pp. 47–55, 2008.

    Article  Google Scholar 

  33. T. Krishnamohan and K. C. Saraswat, “High mobility Ge and III-V materials and novel device structures for high performance nanoscale MOSFETS” in ESSDERC 2008, Edinburgh, UK, pp. 38–46, 2008.

    Google Scholar 

  34. M. V. Fischetti, T. P. O'Regan, S. Narayanan, C. Sachs, S. Jin, J. Kim, and Y. Zhang, “Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10-nm gate-length,” IEEE Transactions on Electron Devices, vol. 54, pp. 2116–36, 2007.

    Article  Google Scholar 

  35. T. Krishnamohan, D. Kim, T. V. Dinh, A.-T. Pham, B. Meinerzhagen, C. Jungemann, and K. C. Saraswat, “Comparison of (001), (110) and (111) uniaxial- and biaxial-strained-Ge and strained-Si PMOS DGFETs for all channel orientations: Mobility enhancement, drive current, delay and off-state leakage” presented at International Electron Devices Meeting (IEDM), San Francisco, CA, 2008.

    Google Scholar 

  36. D. Kim, T. Krishnamohan, and K. C. Saraswat, “Performance evaluation of uniaxial- and biaxial-strained In(x)Ga(1−x)As NMOS DGFETs” in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 101–4, 2008.

    Google Scholar 

  37. A. Nainani, D. Kim, T. Krishnamohan, and K. C. Saraswat, “Hole mobility and its enhancement with strain for technologically relevant III-V semiconductors” presented at 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD′09), San Diego, CA, 2009.

    Google Scholar 

  38. P. P. Ruden, M. Shur, D. K. Arch, R. R. Daniels, D. E. Grider, and T. E. Nohava, “Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors,” IEEE Transactions on Electron Devices, vol. 36, pp. 2371–9, 1989.

    Article  Google Scholar 

  39. A. Nainani, S. Raghunathan, D. Witte, M. Kobayashi, T. Irisawa, T. Krishnamohan, K. C. Saraswat, B. R. Bennett, M. Ancona, and J. B. Boos, “Engineering of strained III-V heterostructures for high hole mobility” presented at 2009 IEEE International Electron Devices Meeting, Baltimore, MD, 2009.

    Google Scholar 

  40. G. C. Osbourn, “Electron and hole effective masses for two-dimensional transport in strained-layer superlattices,” Superlattices and Microstructures, vol. 1, pp. 223–6, 1985.

    Article  Google Scholar 

  41. M. Jaffe, J. E. Oh, J. Pamulapati, J. Singh, and P. Bhattacharya, “In-plane hole effective masses in InxGa1-xAs/Al0.15Ga0.85As modulation-doped heterostructures,” Applied Physics Letters, vol. 54, pp. 2345–6, 1989.

    Article  Google Scholar 

  42. M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jefferies, T. Martin, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith, M. J. Uren, D. J. Wallis, P. J. Wilding, and R. Chau, “High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC = 0.5 V) logic applications” in Technical Digest—2008 IEEE International Electron Devices (IEDM), pp. 727–30, 2008.

    Google Scholar 

  43. B. R. Bennett, M. G. Ancona, J. B. Boos, C. B. Canedy, and S. A. Khan, “Strained GaSb/AlAsSb quantum wells for p-channel field-effect transistors,” Journal of Crystal Growth, vol. 311, pp. 47–53, 2008.

    Article  Google Scholar 

  44. B. R. Bennett, M. G. Ancona, J. B. Boos, and B. V. Shanabrook, “Mobility enhancement in strained p-InGaSb quantum wells,” Applied Physics Letters, vol. 91, pp. 042104, 2007.

    Article  Google Scholar 

  45. G. Bastard, Wave Mechanics applied to semiconductor heterostructures. New York, Halsted Press, Wiley, 1988.

    Google Scholar 

  46. T. Krishnamohan, D. Kim, C. Nguyen, C. Jungemann, Y. Nishi, and K. C. Saraswat, “High-mobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: Simulations,” IEEE Transactions on Electron Devices, vol. 53, pp. 1000–9, 2006.

    Article  Google Scholar 

  47. T. Krishnamohan, D. Kim, C. Jungemann, Y. Nishi, and K. C. Saraswat, “Strained-Si, relaxed-Ge or strained-(Si)Ge for future nanoscale p-MOSFETs?” in Digest of Technical Papers—2006 Symposium on VLSI Technology, pp. 144–5, 2006.

    Google Scholar 

  48. F. A. T. M and A. V. K., “Quantum engineering of nanoelectronic devices: The role of quantum confinement on mobility degradation,” Microelectronics Journal, vol. 32, pp. 679–86, 2001.

    Article  Google Scholar 

  49. K. Uchida and S.-I. Takagi, “Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors,” Applied Physics Letters, vol. 82, pp. 2916, 2003.

    Article  Google Scholar 

  50. J. Tersoff, “Schottky barriers and the continuum of gap states,” Physical Review Letters, vol. 52, pp. 465–8, 1984.

    Article  Google Scholar 

  51. A. Pethe and K. C. Saraswat, “High-mobility, low parasitic resistance Si/Ge/Si heterostructure channel Schottky source/drain PMOSFETs” in 65th Device Research Conference, 2007, pp. 55–6.

    Google Scholar 

  52. A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, “Fermi-level pinning and charge neutrality level in germanium,” Applied Physics Letters, vol. 89, pp. 252110-1-3, 2006.

    Article  Google Scholar 

  53. H. H. Wieder, “Surface and interface barriers of InxGa1-xAs binary and ternary alloys,” Journal of Vacuum Science and Technology B, vol. 21, pp. 1915–9, 2003.

    Article  Google Scholar 

  54. A. Khakifirooz and D. A. Antoniadis, “MOSFET performance scaling. Part I. Historical trends,” IEEE Transactions on Electron Devices, vol. 55, pp. 1391–400, 2008.

    Article  Google Scholar 

  55. A. Khakifirooz and D. A. Antoniadis, “MOSFET performance scaling-Part II: Future directions,” IEEE Transactions on Electron Devices, vol. 55, pp. 1401–8, 2008.

    Article  Google Scholar 

  56. D. A. Antoniadis, I. Aberg, C. Ni Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, “Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations,” IBM Journal of Research and Development, vol. 50, pp. 363–76, 2006.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Center for Integrated Systems, Department of Electrical Engineering, Stanford University, 94305, Stanford, CA, USA

    Tejas Krishnamohan

Authors
  1. Tejas Krishnamohan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Donghyun Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Krishna C. Saraswat
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Tejas Krishnamohan .

Editor information

Editors and Affiliations

  1. College of Nanoscale Science &, University at Albany - SUNY, Fuller Road 255, Albany, 12203, U.S.A.

    Serge Oktyabrsky

  2. Birck Nanotechnology Center, Purdue University, W. State Street 1205, West Lafayette, 47907-2057, U.S.A.

    Peide Ye

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Krishnamohan, T., Kim, D., Saraswat, K. (2010). Properties and Trade-Offs of Compound Semiconductor MOSFETs. In: Oktyabrsky, S., Ye, P. (eds) Fundamentals of III-V Semiconductor MOSFETs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-1547-4_2

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-1547-4_2

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-1546-7

  • Online ISBN: 978-1-4419-1547-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation