3D Stacking of DRAM on Logic

Abstract

An ever-increasing number of transistors are being placed onto silicon dies in both small and large computing systems. The shrinking of the transistors on these chips has allowed an increasingly large amount of computing power to be brought to smaller and smaller devices. There have been many advances in computing architectures that have allowed this pace to continue. Examples can be seen through the development of combining numerous application processors into MPSoCs (multiprocessor systems on a chip) as well as techniques like hardware multithreading. Through the increase in both complexity of chip designs and the number of those chips occupying a single die, our computers now require greater bandwidth to an ever increasing amount of system DRAM memory. By optimizing these systems with TSVs, one can alleviate this memory bottleneck while simultaneously reducing the overall energy consumption of the complete computing platform.