Simultaneous Input Vector Control and Circuit Modification

  • Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri


Leakage power currently comprises a large fraction of the total power consumption of an IC. Techniques to minimize leakage have been researched widely. However, most approaches to reducing leakage have an associated performance penalty. In this chapter, we present an approach that minimizes leakage by simultaneously modifying the circuit while deriving the input vector that minimizes leakage. In our approach, we selectively modify a gate so that its output (in sleep mode) is in a state that helps minimize the leakage of other gates in its transitive fanout. Gate replacement is performed in a slack-aware manner, to minimize the resulting delay penalty. One of the major advantages of our technique is that we achieve a significant reduction in leakage without increasing the delay of the circuit.

The remainder of this chapter is organized as follows: The motivation for this work is described in Sect. 6.3. Section 6.4 discusses some previous work in this area. In Sect. 6.5, we describe our method to minimize leakage in a circuit through simultaneous input vector control and circuit modification. In Sect. 6.6, we present experimental results, while conclusions and future work are discussed in Sect. 6.7.


Primary Input Area Overhead Sequential Circuit Combinational Circuit Minimum Leakage 
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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleUSA
  2. 2.AustinUSA
  3. 3.HillsboroUSA
  4. 4.College StationUSA
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

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