Accelerating Fault Simulation Using Graphics Processors

  • Kanupriya Gulati
  • Sunil P. Khatri


In this chapter, we explore the implementation of fault simulation on a graphics processing unit (GPU). In particular, we implement a parallel fault simulator. Fault simulation is inherently parallelizable, and the large number of threads that can be computed in parallel on a GPU results in a natural fit for the problemof parallel fault simulation.


Graphic Processing Unit Global Memory Single Instruction Multiple Data Very Large Scale Integration Fault Injection 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Commercial fault simulation tool. Licensing agreement with the tool vendor requires that we do not disclose the name of the tool or its vendor.Google Scholar
  2. 2.
  3. 3.
    NVIDIA Tesla GPU Computing Processor.
  4. 4.
    Abramovici, A., Levendel, Y., Menon, P.: A logic simulation engine. In: IEEE Transactions on Computer-Aided Design, vol. 2, pp. 82–94 (1983)Google Scholar
  5. 5.
    Agrawal, P., Dally, W.J., Fischer, W.C., Jagadish, H.V., Krishnakumar, A.S., Tutundjian, R.: MARS: A multiprocessor-based programmable accelerator. IEEE Design and Test 4 (5), 28–36 (1987)CrossRefGoogle Scholar
  6. 6.
    Amin, M.B., Vinnakota, B.: Workload distribution in fault simulation. Journal of Electronic Testing 10(3), 277–282 (1997)CrossRefGoogle Scholar
  7. 7.
    Amin, M.B., Vinnakota, B.: Data parallel fault simulation. IEEE Transactions on Very Large Scale Integration (VLSI) systems 7(2), 183–190 (1999)CrossRefGoogle Scholar
  8. 8.
    Banerjee, P.: Parallel Algorithms for VLSI Computer-aided Design. Prentice Hall Englewood Cliffs, NJ (1994)Google Scholar
  9. 9.
    Beece, D.K., Deibert, G., Papp, G., Villante, F.: The IBM engineering verification engine. In: DAC ’88: Proceedings of the 25th ACM/IEEE Conference on Design Automation, pp. 218–224. IEEE Computer Society Press, Los Alamitos, CA (1988)Google Scholar
  10. 10.
    Gulati, K., Khatri, S.P.: Towards acceleration of fault simulation using graphics processing units. In: Proceedings, IEEE/ACM Design Automation Conference (DAC), pp. 822–827 (2008)Google Scholar
  11. 11.
    Ishiura, N., Ito, M., Yajima, S.: High-speed fault simulation using a vector processor. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD) (1987)Google Scholar
  12. 12.
    Mueller-Thuns, R., Saab, D., Damiano, R., Abraham, J.: VLSI logic and fault simulation on general-purpose parallel computers. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 446–460 (1993)CrossRefGoogle Scholar
  13. 13.
    Narayanan, V., Pitchumani, V.: Fault simulation on massively parallel simd machines: Algorithms, implementations and results. Journal of Electronic Testing 3(1), 79–92 (1992)CrossRefGoogle Scholar
  14. 14.
    Ozguner, F., Aykanat, C., Khalid, O.: Logic fault simulation on a vector hypercube multiprocessor. In: Proceedings of the third conference on Hypercube concurrent computers and applications, pp. 1108–1116 (1988)Google Scholar
  15. 15.
    Ozguner, F., Daoud, R.: Vectorized fault simulation on the Cray X-MP supercomputer. In: Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers, IEEE International Conference on, pp. 198–201 (1988)Google Scholar
  16. 16.
    Parkes, S., Banerjee, P., Patel, J.: A parallel algorithm for fault simulation based on PROOFS. pp. 616–621. URL
  17. 17.
    Patil, S., Banerjee, P.: Performance trade-offs in a parallel test generation/fault simulation environment. In: IEEE Transactions on Computer-Aided Design, pp. 1542–1558 (1991)Google Scholar
  18. 18.
    Pfister, G.F.: The Yorktown simulation engine: Introduction. In: DAC ’82: Proceedings of the 19th Conference on Design Automation, pp. 51–54. IEEE Press, Piscataway, NJ (1982)Google Scholar
  19. 19.
    Raghavan, R., Hayes, J., Martin, W.: Logic simulation on vector processors. In: Computer-Aided Design, Digest of Technical Papers, IEEE International Conference on, pp. 268–271 (1988)Google Scholar
  20. 20.
    Tai, S., Bhattacharya, D.: Pipelined fault simulation on parallel machines using the circuitflow graph. In: Computer Design: VLSI in Computers and Processors, pp. 564–567 (1993)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.CoppellUSA
  2. 2.Department of Electrical & Computer EngineeringTexas A & M UniversityCollege StationUSA

Personalised recommendations