Abstract
This chapter presents a radiation tolerant combinational circuit design approach, which is based on the clamping action of a diode. This diode clamping-based hardening approach is based on the use of shadow gates, whose task is to protect the primary gate in case it experiences a radiation strike. The gate to be protected is duplicated locally, and a pair of diode connected transistors (or diodes) is connected between the outputs of the original and the shadow gate. These diodes turn on when the voltage across the two gate outputs deviates (during a radiation strike). A methodology is also presented to protect specific gates of the circuit based on electrical masking, in a manner that guarantees radiation tolerance for the entire circuit while keeping the area and delay overhead low. An improved circuit level hardening algorithm is also proposed, to further reduce the delay and area overhead. Note that the diode clamping-based approach is suitable for hardening a circuit against low energy particle strikes.
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References
R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, “A design approach for radiation-hard digital electronics,” in Proc. of the Design Automation Conf., July 2006, pp. 773–778.
R. Garg and S. P Khatri, “A novel, highly SEU tolerant digital circuit design approach,” in Proc. of the Intl. Conf. on Computer Design, Oct. 2008, pp. 14–20.
W. Massengill, M. Alles, and S. Kerns, “SEU error rates in advanced digital CMOS,” in Proc. of the European Conf. on Radiation and Its Effects on Components and Systems, Sep. 1993, pp. 546 – 553.
J. Pickle and J. Blandford, “CMOS RAM cosmic-ray-induced error rate analysis,” IEEE Transactions on Nuclear Science, vol. NS-29, pp. 3962–3967, 1981.
J. Wang, B. Cronquist, and J. McGowan, “Rad-hard/hi-rel FPGA,” in Proc. of the ESA Electronic Components Conf., April 1997, pp. 1–4.
R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, “A design approach for radiation-hard digital electronics,” in Proc. of the Design Automation Conf., July 2006, pp. 773–778.
Q. Zhou and K. Mohanram, “Gate sizing to radiation harden combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155–166, Jan. 2006.
Q. Zhou and K. Mohanram, “Transistor sizing for radiation hardening,” in Proc. of the Intl. Reliability Physics Symposium, April 2004, pp. 310–315.
T. May and M. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Transaction on Electron Devices, vol. ED-26, pp. 2–9, Jan 1979.
B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, and S. Garverick, “An efficient BICS design for SEUs detection and correction in semiconductor memories,” in Proc. of the Conf. on Design Automation and Test in Europe, March 2005, pp. 592–597.
G. Agrawal, L. Massengill, and K. Gulati, “A proposed SEU tolerant dynamic random access memory (DRAM) cell,” in IEEE Transactions on Nuclear Science, Dec. 1994, vol. 41, pp. 2035–2042.
M. Caffrey, P. Graham, E. Johnson, and M. Wirthli, “Single-event upsets in SRAM FPGAs,” in Proc. of the Intl. Conf. on Military and Aerospace Programmable Logic Devices, Sep. 2002, pp. 1–6.
C. Carmichael, E. Fuller, M. Caffrey, P. Blain, and H. Bogrow, “SEU mitigation techniques for Virtex FPGAs in space applicaions,” in Proc. of the Intl. Conf. on Military and Aerospace Programmable Logic Devices, Sep. 1999, pp. 1–8.
S. Whitaker, J. Canaris, and K. Liu, “SEU hardened memory cells for a CCSDIS Reed Solomon encoder,” IEEE Transactions on Nuclear Science, vol. 38, no. 6, pp. 1471–1477, 1991.
M. N. Liu and S. Whitaker, “Low power SEU immune CMOS memory circuits,” IEEE Transactions on Nuclear Science, vol. 36, no. 6, pp. 1679–1684, 1992.
J. S. Cable, E. F. Lyons, M. A. Stuber, and M. L. Burgener, “United States patent 6531739: Radiation-hardened silicon-on-insulator CMOS device, and method of making the same,” Available: http://www.freepatentsonline.com/6531739.html, Nov. 2003, pp. 1-16.
K. Mohanram and N. A. Touba, “Cost-effective approach for reducing soft error failure rate in logic circuits,” in Proc. of the Intl. Test Conf., 2003, pp. 893–901.
T. Heijmen and A. Nieuwland, “Soft-error rate testing of deep-submicron integrated circuits,” in Proc. of the IEEE European Test Symposium, 2006, pp. 247–252.
C. Nagpal, R. Garg, and S. P. Khatri, “A delay-efficient radiation-hard digital design approach using CWSP elements,” in Proc. of the Conf. on Design Automation and Test in Europe, March 2008, pp. 354–359.
P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583– 602, 2003.
J. P. Hayes, I. Polian, and B. Becker, “An analysis framework for transient-error tolerance,” in Proc. of the VLSI Test Symposium, 2007, pp. 249–255.
C. Zhao, S. Dey, and X. Bai, “Soft-spot analysis: Targeting compound noise effects in nanometer circuits,” Design and Test of Computers, vol. 22, no. 4, pp. 362–375, 2005.
C. Zhao and S. Dey, “Improving transient error tolerance of digital VLSI circuits using robustness compiler (ROCO),” in Proc. of the Intl. Symposium on Quality Electronic Design, 2006, pp. 133–140.
S. Mitra, N. Seifert, M. Zhang, and K. Kim, “Robust system design with built-in soft-error resilience,” IEEE Transactions on Computers, vol. 38, pp. 43–52, Feb. 2005.
T. Fukai, Y. Nakahara, M. Terai, S. Koyama, and Y. Morikuni et al., “A 65 nm-node CMOS technology with highly reliable triple gate oxide suitable for power-considered system-on-a-chip,” Proc. of the Symposium on VLSI Technology, pp. 83–84, June 2003.
Q. Lin, M. Ma, T. Vo, J. Fan, X. Wu, R. Li, and X. Li, “Design-for-manufacture for multi-gate oxide CMOS process,” in Proc. of the Intl. Symposium on Quality Electronic Design, 2007, pp. 339–343.
B. Amelifard, F. Fallah, and M. Pedram, “Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment,” in Proc. of the Conf. on Design Automation and Test in Europe, 2006, pp. 995–1000.
Altera Inc., San Jose, CA, “Stratix III programmable power,” May 2007, pp. 1-12, Available: http://www.altera.com/literature/wp/wp-01006.pdf.
L. Nagel, “Spice: A computer program to simulate computer circuits,” in University of California, Berkeley UCB/ERL Memo M520, May 1995.
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit design,” in Proc. of IEEE Custom Integrated Circuit Conf., June 2000, pp. 201–204.
P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, chapter Delay Models and Exact Timing Analysis, pp. 167–189, US Kluwer Academic Publishers, Boston, MA, 1993.
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “SIS: A system for sequential circuit synthesis,” Tech. Rep. UCB/ERL M92/41, Electronics Research Laboratory, Univ. of California, Berkeley, May 1992.
Cadence Design Systems, Inc., San Jose, CA, Envisia Silicon Ensemble Place-and-route Reference Manuals, Nov 1999.
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Garg, R., Khatri, S.P. (2010). Clamping Diode-based Radiation Tolerant Circuit Design Approach. In: Analysis and Design of Resilient VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0931-2_6
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