Abstract
An analysis of the effects of voltage scaling on the radiation tolerance of VLSI systems is presented in this chapter. For this analysis, 3D simulations of radiation particle strikes on the output of an inverter (implemented using DVS and subthreshold design) were performed. The radiation particle strike on an inverter was simulated using Sentaurus-DEVICE for different inverter sizes, inverter loads, supply voltage values, and the energy of the radiation particles. From these 3D simulations, several nonintuitive observations were made, which are important to consider during radiation hardening of such DVS and subthreshold circuits. On the basis of these observations, several guidelines are proposed for radiation hardening of such designs. These guidelines suggest that traditional radiation hardening approaches need to be revisited for DVS and subthreshold designs. A charge collection model for DVS circuits is also proposed, using the results of these 3D simulations. The parameters of this charge collection model can be included in transistor model cards in SPICE, to improve the accuracy of SPICE-based simulations of radiation events in DVS circuits.
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Garg, R., Khatri, S.P. (2010). 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits. In: Analysis and Design of Resilient VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0931-2_5
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DOI: https://doi.org/10.1007/978-1-4419-0931-2_5
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