Low-Power Design Techniques and Test Implications

Chapter

Abstract

This chapter provides a brief overview of the prevalent design techniques for dynamic and leakage power reduction in both logic and memory circuits. It also provides an introduction to power specification format, which allows specification of circuit properties with respect to power dissipation in a consistent manner. Next, it discusses the impact of existing low-power design techniques on test. Finally, it covers the test implications of the post-silicon adaptation approaches for power reduction.

Notes

Acknowledgements

We would like to express our appreciation to Dr. Swaroop Ghosh, Prof. Chris Kim, Mr. Seetharam Narasimhan, and Mr. Rajat Subhra Chakraborty for providing important help with the technical content and presentation of the chapter.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Purdue UniversityWest LafayetteUSA
  2. 2.Case Western Reserve UniversityClevelandUSA

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