Abstract
On-chip interconnects are predicted to be a fundamental issue in designing multi-core chip multiprocessors (CMPs) and system-on-chip (SoC) architectures with numerous homogeneous and heterogeneous cores and functional blocks. To mitigate the interconnect crisis, one promising option is network-on-chip (NoC), where a general purpose on-chip interconnection network replaces the traditional design-specific global on-chip wiring by using switching fabrics or routers to connect IP cores or processing elements. Such packet-based communication networks have been gaining wide acceptance due to their scalability and have been proposed for future CMPs and SoC design. In this chapter, we study the combination of both three-dimensional integrated circuits and NoCs, since both are proposed as solutions to mitigate the interconnect scaling challenges. This chapter will start with a brief introduction on network-on-chip architecture and then discuss design space exploration for various network topologies in 3D NoC design, as well as different techniques on 3D on-chip router design. Finally, it describes a design example of using 3D NoC with memory stacked on multi-core CMPs.
This chapter includes portions reprinted with permission from the following publications: (a) F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, Design and management of 3D chip multiprocessors using network-in-memory, Proceedings of International Symposium on Computer Architecture (2006). Copyright 2006 IEEE. (b) J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, and C. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, Proceedings of International Symposium on Computer Architecture (2007). Copyright 2007 IEEE. (c) P. Dongkook, S. Eachempati, R. Das, A. K. Mishra, Y. Xie, N. Vijaykrishnan, and C. R. Das, Mira: A multi-layered on-chip interconnect router architecture, Proceedings of International Symposium on Computer Architecture (2008). Copyright 2008 IEEE.
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Acknowledgments
Much of the work and ideas presented in this chapter have evolved over several years of working with our colleagues and graduate students, in particular Professor Mahmut Kandemir, Dr. Mazin Yousif from Intel, Chrysostomos Nicopoulos, Thomas Richardson, Feihui Li, Jongman Kim, Dongkook Park, Reetuparna Das, Asit Mishra, and Soumya Eachempati. The research was supported in part by NSF grants, EIA-0202007, CCF-0429631, CNS-0509251, CCF-0702617, CAREER 0093085, and a grant from DARPA/MARCO GSRC.
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Xie, Y., Vijaykrishnan, N., Das, C. (2010). Three-Dimensional Network-on-Chip Architecture. In: Xie, Y., Cong, J., Sapatnekar, S. (eds) Three Dimensional Integrated Circuit Design. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0784-4_8
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