Abstract
The majority of the existing 3D IC research has focused on how to take advantage of the performance, power, smaller form-factor, and heterogeneous integration benefits offered by 3D integration. However, all such advantages will ultimately have to be translatee into cost savings when a design strategy has to be decided. Consequently, system-level cost analysis at the early design stage is imperative to help the decision making on whether 3D integration should be adopted. In this chapter, we discuss the design estimation method for 3D ICs at the early design stage. We also describe a cost analysis model to study the cost implication for 3D ICs and address cost-related problems for 3D IC design.
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Notes
- 1.
The design has open-source design verilog code and synthesis scripts on http://www.opensparc.net. The original T1 chip was fabricated at 90-nm technology, with 300 M transistors and an area of 340 mm2.
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Acknowledgments
The authors would like to thank Dr. Larry Smith from SEMATECH, Dr. Mike Ignatowski from IBM, Dr. Sam Gu from Qualcomm, and Dr. Pol Marchal from IMEC for the valuable discussions and guidance on this research. This work was supported in part by NSF grants of CAREER 0643902 and CCF 0702617, a grant from Qualcomm, and an IBM Faculty Award.
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Dong, X., Xie, Y. (2010). System-Level 3D IC Cost Analysis and Design Exploration. In: Xie, Y., Cong, J., Sapatnekar, S. (eds) Three Dimensional Integrated Circuit Design. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0784-4_10
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