Strain in Electron Devices
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Today’s strain-Si technology has been based on the physics of strain effects on bulk and low-dimensional band structures and carrier transport. Although the strain effects on bulk semiconductors have been studied since the 1950s, and the effects on Si MOSFETs have been discovered and studied since 1980s, strain has never really been adopted in mainstream Si CMOS technology until 2002s by Intel, because before then, the speed of the VLSI/ULSI chips could be boosted just by geometrical scaling, i.e., increasing the transistor density, which now numbers typically at ~109 in a single chip, by shrinking the transistor size. However, this comes with price. Short channel effects significantly degrade the device performance when the transistor size is too small, and the leakage current results in large power dissipation, then the traditional scaling reaches a bottleneck. Strain then as a “performance adder” is eventually adopted. Today, the chips with strained-Si devices (see Fig. 7.1) serve the three dominant markets of computer, communication and consumer electronics and highlight the wide success of this technology in not only high performance but also low cost markets.
KeywordsSiGe Layer Gate Leakage Gate Leakage Current Mobility Enhancement pMOS Device
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