Skip to main content
SpringerLink
Log in

General-Purpose Multi-core Processors

  • Chapter
  • First Online:
Multicore Processors and Systems

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

During the past several decades, the general-purpose microprocessor industry has effectively leveraged Moore’s Law to offer continually increasing single-thread microprocessor performance and compelling new features. However, the amazing increase in performance was not free: many practical design constraints, especially power consumption, were pushed to their limits. The integration of multiple microprocessor cores into CPU chips has improved the capability of the single-CPU chip systems and extended the capability of the multiple-CPU chip systems in a very natural way. General-purpose multi-core processors have brought parallel computing into the mainstream and penetrated markets from laptops to supercomputers. This chapter discusses the history and trends behind this exciting development and future challenges and opportunities in hardware and software. This chapter presents the AMD Opteron™ microarchitecture as a case study in how one company addressed the power, software stack, and infrastructure challenges posed by general-purpose CMP architectures across several product generations.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. Moore. Cramming More Components onto Integrated Circuits. Electronics Magazine, (38)8, April 19, 1965.

    Google Scholar 

  2. B. Sinharoy, R. Kalla, J. Tendler, R. Eickemeyer, and J. B. Joyner. POWER5 System Microarchitecture. IBM Journal of Research & Development, 49(4/5):505–521, July/Sep 2005.

    Article  Google Scholar 

  3. R. Kessler. The Alpha 21264 Microprocessor. IEEE Micro, 19(2):24–36, Mar 1999.

    Article  MathSciNet  Google Scholar 

  4. C. Keltcher, K. McGrath, A. Ahmed, and P. Conway. The AMD Opteron Processor for Shared Memory Multiprocessor systems.IEEE Micro, 23(2):66–76, Mar/April 2003.

    Article  Google Scholar 

  5. M. Flynn, P. Hung, and K. Rudd. Deep Submicron Microprocessor Design Issues. IEEE Micro, (19)4:11–22, July/Aug, 1999.

    Article  Google Scholar 

  6. S. Borkar. Design Challenges of Technology Scaling, IEEE Micro, 19(4):23–29, July/Aug, 1999.

    Article  Google Scholar 

  7. V. Agarwal, M. Hrishikesh, S. Keckler, and D. Burger. Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures. International Symposium on Computer Architecture, pp. 248–259, June 2000.

    Google Scholar 

  8. M. Flynn and P. Hung. Microprocessor Design Issues: Thoughts on the Road Ahead. IEEE Micro, 25(3):16–31, May/June 2005.

    Article  Google Scholar 

  9. V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez. Reducing Power in High-Performance Microprocessors. Design Automation Conference, pp. 732–737, June 1998.

    Google Scholar 

  10. C. Isci, A. Buyuktosunoglu, C. Cher, P. Bose, and M. Martonosi. An Analysis of Efficient Multi-core Global Power Management Policies: Maximizing Performance for a Given Power Budget, International Symposium on Microarchitecture, pp. 347–358, Dec 2006.

    Google Scholar 

  11. R. McDougall and J. Mauro. Solaris Internals: Solaris 10 and OpenSolaris Kernel Architecture. Prentice Hall, 2007.

    Google Scholar 

  12. G. Amdahl. Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities. AFIPS Conference Proceedings, 30:483–485, 1967.

    Google Scholar 

  13. K. Asanovic, R. Bodik, B. Catanzaro, J. Gebis, P. Husbands, K. Keutzer, D. Patterson, W. Plishker, J. Shalf, S. Williams, and K. Yelick. The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report UCB/EECS-2006-183, EECS Department University of California, Berkeley, December 2006.

    Google Scholar 

  14. L. Barroso, K. Gharacharloo, and E. Bugnion. Memory System Characterization of Commercial Workloads. International Symposium on Computer Architecture, pp. 3–14, 1998.

    Google Scholar 

  15. W. Wulf and S. Mckee. Hitting the Memory Wall: Implications of the Obvious. Computer Architecture News, 23(1):20–24, 1995.

    Article  Google Scholar 

  16. J. Laudon, R. Golla, and G. Grohoski. Throughput-oriented Multicore Processors. In S. Keckler, K. Olukotun, and P. Hofstee (Eds.), Multicore Processors and Systems, Springer.

    Google Scholar 

  17. AMD x86-64 Architecture Manuals, http://www.amd.com

  18. S. McFarling. Combining Branch Predictors. WRL Technical Note TN-36, June 1993.

    Google Scholar 

  19. HyperTransport I/O Link Specification, http://www.hypertransport.org/

  20. P. Conway and W. Hughes. The AMD Opteron Northbridge Architecture. IEEE Micro, 27(2):10–21, Mar–Apr 2007.

    Article  Google Scholar 

  21. J. Hennessy and D. Patterson. Computer Architecture: a Quantitative Approach. Fourth Edition, Morgan Kaufmann, 2007.

    Google Scholar 

  22. “AMD-V Nested Paging v1.0,” white paper, July 2008, http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf

  23. D. Culler, J. Pal Singh, and A. Gupta, Parallel Computer Architecture, a Hardware/Software Approach. Morgan Kaufmann, 1999.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Advanced Micro Devices Inc., Sunnyvale, CA, USA

    Chuck Moore & Pat Conway

Authors
  1. Chuck Moore
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Pat Conway
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Chuck Moore .

Editor information

Editors and Affiliations

  1. College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A.

    Stephen W. Keckler

  2. Dept. Electrical Engineering, Stanford University, Stanford, 94305-9510, U.S.A.

    Kunle Olukotun

  3. IBM Software Group, Burnet Rd. 11501, Austin, 78758, U.S.A.

    H. Peter Hofstee

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer-Verlag US

About this chapter

Cite this chapter

Moore, C., Conway, P. (2009). General-Purpose Multi-core Processors. In: Keckler, S., Olukotun, K., Hofstee, H. (eds) Multicore Processors and Systems. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0263-4_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-0263-4_6

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-0262-7

  • Online ISBN: 978-1-4419-0263-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation