Clocking and Variation
As process technology continues to scale, increasing numbers of transistors are integrated onto a single processor die, providing higher levels of performance and additional features (Fig.1.1). However, the unwanted side-effect of this increased integration is the worsening of variations of all types: static process variations resulting from reduced device dimensions and dynamic voltage and temperature variations. At the same time, transistor degradation and early-life failure are always concerns, but becoming more critical as the number of devices increases.
The clock network on a microprocessor plays a special role in how the processor tolerates variations of all types. On one hand, the clock is very sensitive to variations, and any fluctuations in the clock due to variations can directly impact the frequency of the processor. Thus, it is absolutely critical to design the clock network in such a way that the impact of variations is reduced. On the other hand, variations also present an opportunity in clock network design. Because of the global nature of the clock, it can be used as a “knob” for tolerating variations or reducing their impacts. In this chapter, we will discuss both challenges and opportunities that variations present to clock network design.
KeywordsCritical Path Transparency Window Pipeline Stage Voltage Droop Clock Edge
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