Phase Noise and Jitter

Abstract

In this chapter we examine variations that occur in the edge locations of the clock signal in a synchronous system. These edge variations are referred to in the time domain as jitter and in the frequency domain as phase noise. We also describe the various mechanisms that can cause these non-idealities and present techniques to analyze their individual contributions to total jitter. We begin by defining precisely what we mean by jitter and relate the various types of jitter to one another. Next, we explore the relationship between the time domain representation of timing error as jitter and the frequency domain representation of timing error as phase noise. The fundamental relationship between phase jitter (also denoted as absolute jitter) and phase noise will provide a useful basis for analysis of all types of jitter via simple frequency domain filter functions.

Building on this frequency domain foundation, we explore the jitter behavior of the phase locked loop (PLL) system that is most often used to generate on-chip clock signals. We utilize a control system block diagram model [1] that allows for simple analysis to determine how the PLL dynamics filter the noise sources internal to the PLL (intrinsic noise) as well as how the PLL reacts to noise sources externalto the PLL (extrinsic noise).