Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

  • Haykel Ben Jamaa
  • Bahman Kheradmand Boroujeni
  • Giovanni De Micheli
  • Yusuf Leblebici
  • Christian Piguet
  • Alexandre Schmid
  • Milos Stanisavljevic
Chapter

Abstract

As already explained in the introduction to Chap. , the development of economically feasible nanoelectronic systems requires a tight interplay between materials and fabrication technologies on the one hand and design technologies on the other. In particular, it is quite essential to explore circuit-level measures to mitigate the limitations of process variations (PVs), leakage, and reduced device reliability and, finally, to explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics. This chapter largely deals with some of these key questions that relate to design technologies for nanoelectronic systems.

Keywords

Convolution 

References

  1. 1.
    Holmes JD et al (2000) Control of thickness and orientation of solution-grown silicon nanowires. Science 287(5457):1471–1473CrossRefGoogle Scholar
  2. 2.
    Luo Y et al (2002) Two-dimensional molecular electronics circuits. Chem Phys Chem 3: 519–525CrossRefGoogle Scholar
  3. 3.
    DeHon A (2005) Design of programmable interconnect for sublithographic programmable logic arrays. In: International symposium on field-programmable gate arrays, Monterey, CA, 2005, pp 127–137Google Scholar
  4. 4.
    Choi Y-K et al (2002) A spacer patterning technology for nanoscale CMOS. IEEE Trans Electron Devices 49(3):436–441CrossRefGoogle Scholar
  5. 5.
    Cerofolini GF (2006) Search for realistic limits to computation. II. The technological side Appl Phys A 86(1):31–42Google Scholar
  6. 6.
    Moselund KE et al (2007) Cointegration of gate-all-around MOSFETs and local silicon-on-insulator optical waveguides on bulk silicon. IEEE Trans Nanotechnol 6(1):118–125CrossRefGoogle Scholar
  7. 7.
    Abadir MS, Reghbati HK (1983) Functional testing of semiconductor random access memories. ACM Comput Surv 15(3):175–198CrossRefGoogle Scholar
  8. 8.
    Ben Jamaa MH et al (2008) Variability-aware design of multi-level logic decoders for nanoscale crossbar memories. IEEE Trans Comput Aided Des 27(11):2053–2067CrossRefGoogle Scholar
  9. 9.
    Adams RD (2003) High performance memory testing. Kluwer, DordrechtGoogle Scholar
  10. 10.
    Ben Jamaa MH et al (2008) A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. To appear in ASP-DACGoogle Scholar
  11. 11.
    International Technology Roadmap for Semiconductors (2006) ITRS URL: http://www.itrs.net/Links/2007ITRS/Home2007.html. Accessed 12 Nov 2008
  12. 12.
    Strojwas A et al (1996) Manufacturability of low power CMOS technology solutions. In: Proceedings of international symposium on low power electronics and design (ISLPED), San Diego, CA, pp. 225–232Google Scholar
  13. 13.
    Eisele M, Berthold J, Schmitt-Landsiedel D, Mahnkopf R (1996) The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. In: Proceedings of international symposium on low power electronics and design (ISLPED), San Diego, CA, pp. 237–242Google Scholar
  14. 14.
    Bowman KA, Tang X, Eble JC, Meindl JD (2000) Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. IEEE J Solid State Circuits 35:1186–1193CrossRefGoogle Scholar
  15. 15.
    Bowman K et al (2002) Impact of die-to-die and within die parameter fluctuation on the maximum clock frequency distribution for gigascale integration. IEEE J Solid State Circuits 183–190Google Scholar
  16. 16.
    Suaris P, Kgil T, Bowman KA, De V, Mudge TN (2005) Total power-optimal pipelining and parallel processing under process variations in nanometer technology. In: Proceedings of the 2005 IEEE/ACM international conference on computer-aided design (ICCAD), San Diego, CA, pp 535–540Google Scholar
  17. 17.
    Bowman KA, Austin BL, Eble JC, Tang X, Meindl JD (1999) A physical alpha-power law MOSFET model. IEEE J Solid State Circuits 34:1410–1414CrossRefGoogle Scholar
  18. 18.
    Cao Y, Clark LT (2005) Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. In: Proceedings of DAC, pp 658–663Google Scholar
  19. 19.
    Bult K (2005) Scaling effects in analog design in deep sub-micron CMOS, Lecture Notes: Advanced CMOS Circuit Design, Mead Education, 2005Google Scholar
  20. 20.
    HSPICE User’s Manual (1995) Meta-Software IncGoogle Scholar
  21. 21.
    Ho R et al (2001) The future of wires. IEEE Proc 89(4):490–503CrossRefGoogle Scholar
  22. 22.
    Papoulis A, Pillai SU (2002) Probability, random variables and stochastic processes, 4th edn. McGraw-Hill, New YorkGoogle Scholar
  23. 23.
    Friedberg P et al (2005) Modeling within-die spatial correlation effects for process-design co-optimization. In: Proceedings of international symposium on quality electronic design, pp 516–521Google Scholar
  24. 24.
    Stolk PA, Widdershoven FP, Klaassen DBM (1998) Modeling statistical dopant fluctuations in MOS transistors. IEEE Trans Electron Devices 45(9):1960–1971CrossRefGoogle Scholar
  25. 25.
    Agarwal A, Blaauw D, Zolotov V (2003) Statistical timing analysis for intra-die process variations with spatial correlations. In: Proceedings of international conference on computer aided design, pp 900–907Google Scholar
  26. 26.
    Le J, Li X, Pileggi LT (2004) STAC:statistical timing analysis with correlation. In: Proceedings of design automation conference, pp 343–348Google Scholar
  27. 27.
    Frank DJ, Solomon P, Reynolds S, Shin J (1997) Supply and threshold voltage optimization for low power design. In: Proceedings of international symposium on low power electronics and design (ISLPED), San Diego, CA, pp 317–322Google Scholar
  28. 28.
    Gronowski PE, Bowhill WJ, Preston RP, Gowan MK, Allmon RL (1998) High-performance microprocessor design. IEEE J Solid State Circuits 33:676–686CrossRefGoogle Scholar
  29. 29.
    Hojo T (1931) Distribution of the median, quartiles and interquartile distance in samples from a normal population. Biometrika 23:315–360Google Scholar
  30. 30.
    Keeping ES (1995) Introduction to statistical inference. Dover, New YorkGoogle Scholar
  31. 31.
    Moore PG (1956) The estimation of the mean of a censored normal distribution by ordered variables. Biometrika 43:482–485MathSciNetMATHGoogle Scholar
  32. 32.
    Chishti Z, Vijaykumar TN (2008) Optimal power/performance pipeline depth for SMT in scaled technologies. IEEE Trans Comput 69–81Google Scholar
  33. 33.
    Asenov A (2007) Simulation of statistical variability in nano MOSFETs. In: Proceedings of IEEE symposium on VLSI technology, pp 86–87Google Scholar
  34. 34.
    Das A et al (2007) Mitigating the effects of process variations: architectural approaches for improving batch performance. In: Proceedings of 34th international symposium on computer architecture (ISCA)Google Scholar
  35. 35.
    Karnik T, Borkar S, De V (2004) Probabilistic and variation-tolerant design: key to continued moore’s law. Invited talk in ACM/IEEE Int’l TAU Workshop on Timing IssuesGoogle Scholar
  36. 36.
    Yamaoka M et al (2004) Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology. In: Proceedings of symposium on VLSI circuits, pp 288–291Google Scholar
  37. 37.
    Vittoz E (2004) Weak inversion for ultimate low-power logic. In: Piguet C (ed) Chapter 16 in Low-power electronics design, CRC Press, Boca RatonGoogle Scholar
  38. 38.
    Calhoun BH et al (2005) Modeling and sizing for minimum energy operation in sub-threshold circuits. JSSC 40(9):1778–1786MathSciNetGoogle Scholar
  39. 39.
    Zhai B et al (2006) A 2.60pJ/Inst subthreshold sensor processor for optimal energy efficiency. VLSI Ckts SympGoogle Scholar
  40. 40.
    Verma N, Chandrakasan AP (2007) A 65nm 8T sub-VT SRAM employing sense-amplifier redundancy. In: International solid state circuits conference (ISSCC), pp 328–329 Google Scholar
  41. 41.
    Kwong J et al (2008) A 65nm sub-VT microcontroller with integrated SRAM and switched-capacitor DC–DC converter. In: International solid state circuits conference (ISSCC), pp 318–319Google Scholar
  42. 42.
    Zhai B et al (2005) Analysis and mitigation of variability in subthreshold design. In: Proceedings of international symposium on low power electronics and design (ISLPED05), San Diego, CAGoogle Scholar
  43. 43.
    Ryan JF et al (2007) Analyzing and modeling process balance for sub-threshold circuit design. In: GLSVLSI07 Proceedings of Great Lakes Symposium on VLSI Design Google Scholar
  44. 44.
    De V et al (2001) Techniques for leakage power reduction. In: Chandrakasan A, Bowhill W, Fox F (eds) Design of high-performance microprocessor circuits. IEEE Press, Piscataway, NJ, pp 46–62Google Scholar
  45. 45.
    Calhoun BH, Chandrakasan AP (2006) Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering. JSSC06 41(1):238–245Google Scholar
  46. 46.
    Tschanz J et al (2002) Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. JSSC IEEE Journal of Solid-State Circuits vol. 37Google Scholar
  47. 47.
    Jayakumar N, Khatri SP (2005) A variation-tolerant sub-threshold design approach. In: DAC, pp 716–719Google Scholar
  48. 48.
    Singh N et al (2006) High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett 27(5):383–386CrossRefGoogle Scholar
  49. 49.
    Frei James et al (2004) Body effect in Tri- and Pi-Gate SOI MOSFETs. IEEE Electron Device Lett 25(12):813–815CrossRefGoogle Scholar
  50. 50.
    Chaudhry A, Kumar MJ ( 2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliability 4(1): 99–109CrossRefGoogle Scholar
  51. 51.
    von Arnim K et al (2007) A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM. In: Symposium on VLSI technology digest of technical papers, pp 106–107Google Scholar
  52. 52.
    Choi J-H, Murthy J, Roy K (2007) The effect of process variation on device temperature in FinFET circuits. In: Proceedings of the 2005 IEEE/ACM international conference on computer-aided design (ICCAD), San Diego, CA, pp 747–751Google Scholar
  53. 53.
    Cho KeunHwi et al (2007) Temperature-dependent characteristics of cylindrical gate-all-around twin silicon nanowire MOSFETs (TSNWFETs). IEEE Electron Device Lett 28(12):1129–1131CrossRefGoogle Scholar
  54. 54.
    Cho GR, Chen T (2004) Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans CAD Integrated Circuits Syst 23(2):229–242MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Haykel Ben Jamaa
    • 1
  • Bahman Kheradmand Boroujeni
    • 1
  • Giovanni De Micheli
    • 1
  • Yusuf Leblebici
    • 1
  • Christian Piguet
    • 2
  • Alexandre Schmid
    • 1
  • Milos Stanisavljevic
    • 1
  1. 1.Microelectronic Systems LabEPFL – Swiss Federal Institute of TechnologyLausanneSwitzerland
  2. 2.CSEM – Swiss Center for Electronics and Microtechnology Inc.,NeuchâtelSwitzerland

Personalised recommendations