Embedding Multi-Task Address-Event-Representation Computation

  • Carlos Luján-Martínez
  • Alejandro Linares-Barranco
  • Gabriel Jiménez
  • Antón Civit
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 38)


Address-Event-Representation, AER, is a communication protocol that is intended to transfer neuronal spikes between bioinspired chips. There are several AER tools to help to develop and test AER based systems, which may consist of a hierarchical structure with several chips that transmit spikes among them in real-time, while performing some processing. Although these tools reach very high bandwidth at the AER communication level, they require the use of a personal computer to allow the higher level processing of the event information. We propose the use of an embedded platform based on a multi-task operating system to allow both, the AER communication and processing without the requirement of either a laptop or a computer. In this paper, we present and study the performance of an embedded multi-task ER tool, connecting and programming it for processing Address-Event information from a spiking generator.


Address-Event-Representation AER tool embedded AER computation 


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  1. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, et al., “AER building blocks for multi-layer multi-chip neuromorphic vision systems”. Neural Information rocessing Systems Conference, 2005.Google Scholar
  2. 2.
    M. Sivilotti,, “Wiring considerations in analog VLSI systems, with application to field programmable networks”. PhD thesis, California Institute of Technology asadena, CA, USA, 1991.Google Scholar
  3. A. Cohen, R. Douglas, C. Koch, et al., Report to the National Science Foundation: Workshop on Neuromorphic Engineering, 2001.Google Scholar
  4. M. Mahowald, “VLSI analogs of neuronal visual processing: a synthesis of form and function”. PhD thesis, California Institute of Technology, 1992.Google Scholar
  5. K. Boahen, “Communicating neuronal ensembles between neuromorphic chips”, Neuromorphic Systems Engineering, 1998.Google Scholar
  6. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, and B. Linares- Barranco, “An arbitrary kernel convolution AER-transceiver chip for real-time image filtering. Circuits and Systems”, ISCAS 2006. Proceedings. 2006.Google Scholar
  7. M. Oster, and Liu, “A winner-take-all spiking network with spiking inputs”, IEEE Conference Electronics, Circuits and Systems, pp. 203–206, 2004.Google Scholar
  8. H. Riis, and P. Hafliger, “Spike based learning with weak multi-level static memory. Circuits and Systems”, 2004. ISCAS’04, 2004.Google Scholar
  9. P. Lichtsteiner, and T. Delbruck, “64$×$64 Event-driven logarithmic temporal derivative silicon retina”. IEEE Workshop on Charge-Coupled Devices and Advanced mage Sensors, pp. 157–160, 2005.Google Scholar
  10. A. Linares-Barranco, F. Gómez-Rodríguez, A. Jiménez-Fernández, et al., “Using FPGA for visuo-motor control with a silicon retina and a humanoid robot”, IEEE International Symposium on Circuits and Systems, pp. 1192–1195, 2007.Google Scholar
  11. 11.
    A. Linares-Barranco, A. Jimenez-Fernandez, R. Paz-Vicente, et al., “An AER-based actuator interface for controlling an anthropomorphic robotic hand”, LNCS, 4528:479, 2007.Google Scholar
  12. A. Jimenez-Fernandez, R. Paz-Vicente, M. Rivas, et al., “AER-based robotic closed-loop control system”, IEEE International Symposium on Circuits and Systems, pp. 1044–1047, 2008.Google Scholar
  13. T. Delbruck, and P. Lichtsteiner, “Fast sensory motor control based on event-based hybrid neuromorphic-procedural system”, IEEE International Symposium on Circuits and Systems, pp. 845–848, 2007.Google Scholar
  14. T. Teixeira, E. Culurciello, J. Park, et al., “Address-event imagers for sensor networks: evaluation and modeling”, International conference on Information processing in sensor networks, pp. 458–466, 2006.Google Scholar
  15. 15.
    D. Bauer, A. Belbachir, N. Donath, et al., “Embedded vehicle speed estimation system using an asynchronous temporal contrast vision sensor”, EURASIP Journal on Embedded Systems, 2007(1):34–34.Google Scholar
  16. 16.
    A. Linares-Barranco, G. Jimenez-Moreno, B. Linares-Barranco, and A. Civit-Balcells, “On algorithmic rate-coded AER generation”, IEEE Transactions on Networks, 17(3):771–788, 2006.CrossRefGoogle Scholar
  17. 17.
    M. Oster, A. Whatley, et al., “A hardware/software framework for real-time spiking systems”, Int. Conf. on Artificial Neural Networks, 3696:161–166, 2005.Google Scholar
  18. 18.
    E. Chicca, A.M. Whatley, P. Lichtsteiner, et al., “A multichip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity”, IEEE Transactions on Circuits and Systems, 54(5):981–993, 2007.CrossRefGoogle Scholar
  19. P. Lichtsteiner, C. Posch, T. Delbruck, “A 128 X 128 120db 30mw asynchronous vision sensor that responds to relative intensity change. Solid-State Circuits”, IEEE International Conference Digest of Technical Papers, pp. 2060–2069, 2006.Google Scholar
  20. R. Berner, T. Delbruck, A. Civit-Balcells, and A. Linares-Barranco, “A 5 Meps $100 USB 2.0 address-event monitor-sequencer interface”, IEEE International Symposium on Circuits and Systems, 2007.Google Scholar
  21. Intel-Press, Intel PXA255 Processor Developer’s Manual, volume 278693-002. Intel- Press, 2004.Google Scholar
  22. 22.
    K. Boahen, and A. Andreou, “A contrast sensitive silicon retina with reciprocal synapses”, Advances in Neural Information Processing Systems, 4:764–772, 1992.Google Scholar
  23. 23.
    E. Culurciello, R. Etienne-Cummings and K. Boahen, “A biomorphic digital image sensor”. IEEE Journal of Solid-State Circuits, 38(2):281–294, 2003.CrossRefGoogle Scholar
  24. R. Paz, F. Gomez-Rodriguez, M. Rodriguez, et al., “Test infrastructure for addressevent- representation communications”, Work-Conference on Artificial Neural Networks (IWANN’2005). LNCS, pp. 518–526, 2005.Google Scholar
  25. F. Gomez-Rodriguez, R. Paz, L. Miro, et al., “Two hardware implementations of the exhaustive synthetic AER generation method”. Computational Intelligence and Bioinspired Systems. LNCS, 3512:534–540, 2005.Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2009

Authors and Affiliations

  • Carlos Luján-Martínez
    • 1
  • Alejandro Linares-Barranco
    • 1
  • Gabriel Jiménez
    • 1
  • Antón Civit
    • 1
  1. 1.Depatment Arquitectura y Tecnología de ComputadoresUniversidad de SevillaSevillaSpain

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