NoC Support for Reliable On-Chip Memories
One of the key elements in MPSoCs that are affected by variability in sub-micron technologies are on-chip memories (Wang et al., DATE, 2005). The on-chip memories are especially susceptible to Single Event Upsets (SEUs) such as soft errors, as the transient noise sources can flip the bits in the memory cells. Since the memories store the instructions and data that are used by the processors, having permanent or temporary failures in memories can result in complete failure of the system. Current memories already include extensive mechanisms to correct transient single-bit errors, e.g., by using error-correcting codes such as Hamming code (Xiao et al., IEEE Transactions on Computer, 1996) in the memory arrays. However, these mechanisms are expensive and the overhead in area, power, and delay to be implemented massively inside memories to automatically recover from multi-bit errors would be very high (Wang et al., DATE, 2005). Hence, suitable system-level support to provide efficient fault-tolerant mechanisms for memories will be mandatory to ensure proper operation of future MPSoC designs.
KeywordsFault Tolerance Main Memory Critical Data Soft Error Network Inter
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