Conclusions

This book analyzed, described the design, and presented the test results of Analog-to-Digital Converters employing the three main highspeed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one were reviewed, and the techniques usually employed to improve their performance were presented. It was shown that the linearity of those converters is mainly limited by the offset voltages of the pre-amplifiers, folding circuits and latched comparators. In CMOS technologies, the utilization of offset reduction techniques is mandatory to achieve high frequency operation with low power dissipation and occupied area. The two most widely used techniques, averaging and offset sampling, were thoroughly examined and characterized in this book.

An overview of the relevant conclusions and novel contributions made throughout this book will now be presented.