Averaging Technique – DC Analysis and Termination

As explained in the previous chapter, high-speed flash ADCs usually employ differential pairs as preamplifying stages before the comparators. In folding and interpolation ADCs there are analog preprocessing stages — folding circuits — whose differential pairs define the zero crossing locations. The mismatches in the elements of those circuits cause deviations on the location of the zero crossings, thus having a direct impact on the linearity of the ADC.

The situation without averaging was discussed in section 1.6.2: the location of each zero crossing is determined only by the mismatches between the two transistors and the load resistors of one differential pair. Moreover, the location of different zero crossings are uncorrelated random variables. It was also shown that the offset voltage is related to the area of the components: to lower it, larger devices must be used which, in turn, increases parasitic capacitances, leading to a larger power dissipation and input capacitance or to the reduction of the maximum operating frequency.