Advertisement

Compact Modeling of Double Gate MOSFET for IC Design

  • Marina Reyboz
  • Olivier Rozeau
  • Thierry Poiroux

To take advantage of the double gate MOSFET (DGMOS) architecture with independent driven gates, designers need compact models to imagine new circuits. A model is a description of the device electrical behavior. Thus, the electrostatics part is put in equation, equation's Poisson with Boltzmann or Fermi-Dirac statistics is solved and a transport phenomenon is added: statistical or quantum. A compact model is a simplified model, which allows designs with a lot of transistors. Criteria of a good compact model are simple equations, short computing time, few fitting parameters and predictive. From a circuit design point of view, the computing time is a very significant parameter, as consequence physical models using non-optimized numerical resolutions are not adapted.

They are various methods of modeling a MOS transistor. The main difference is the way of solving equations. The issue is that there is no exact solution of equation's Poisson. Consequently, different options exist: surface potential, charge or threshold voltage approaches.

Keywords

Threshold Voltage Gate Voltage Strong Inversion Subthreshold Slope Weak Inversion 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Y. Taur, “An Analytical Solution to a Double Gate MOSFET with Undoped Body,” IEEE Electron Device Letters, vol.21, no.5, pp. 245–247, May 2000.CrossRefGoogle Scholar
  2. 2.
    Y. Taur, “Analytical Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFET,” IEEE Transaction on Electron Devices, vol. 48, no. 12, pp. 2861–2869, December 2001.CrossRefGoogle Scholar
  3. 3.
    Y. Taur, X. Liang, W. Wang and H. Lu, “A Continuous, Analytical Drain-Current Model for DG MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107–109, February 2004.CrossRefGoogle Scholar
  4. 4.
    M. Chan, T. Y. Man, J. He, X. Xi, C. H. Lin, X. Lin, P. K. Ko, A. M. Niknejad and C. Hu, “Quasi-2D Compact Modeling for Double Gate MOSFET”, in Proceeding of Workshop on Compact Modeling, Nanotech 2004, pp. 108–113, Boston, MA, March 7–11, 2004.Google Scholar
  5. 5.
    J. He, X. Xi, M. Chan, A. Niknejad and C. Hu, “A Non-Charge-Sheet Analytic theory for Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poisson's Equation using SPP Approach,” in Proceeding of Workshop on Compact Modeling, Nanotech 2004, pp. 124–127, Boston, MA, March 7–11, 2004.Google Scholar
  6. 6.
    G. Baccarani, “A Compact Double-Gate MOSFET Model Comprising Quantum-Mechanical and Nonstatc Effects,” IEEE Transaction on Electron Devices, vol. 46, no. 8, pp. 1656–1666, August 1999.CrossRefGoogle Scholar
  7. 7.
    T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O'uchi and H. Koike, “Capacitance Model for Four-Terminal DG MOSFETs,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 800–803, Boston, MA, May 9–11, 2006.Google Scholar
  8. 8.
    J. M. Sallèse, F. Krummenacher, F. Prégaldiny, C. Lallement, A.S. Roy and C. C. Enz, “A Design Oriented Charge-Based Current Model for DG MOSFET and its Correlation with the EKV Formalism,” Solid-State Electronics, vol. 49, no. 3, pp. 485–489, March 2005.CrossRefGoogle Scholar
  9. 9.
    F. Prégaldiny, F. Krummenacher, J.-M. Sallese, B. Diagne and C. Lallement, “A Closed-form Compact model for Symmetric Double-Gate (DG) MOSFETs,” MOS-AK Meeting, Grenoble, France, September 16th 2005.Google Scholar
  10. 10.
    A.S. Roy, J. M. Sallèse and C. C. Enz, “A Closed-Form Charge-Based Expression for Drain Current for Symmetric and Asymmetric Double Gate MOSFET,” in Proceeding of the 35th European Solid-State Device Research Conference, ESSDERC 2005, Grenoble, France, pp. 149–152, September 12–16, 2005.Google Scholar
  11. 11.
    F. Prégaldiny, F. Krummenacher, J. M. Sallese, B. Diagne and C. Lallement, “An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 686–691, Boston, MA, May 9–11, 2006.Google Scholar
  12. 12.
    G. Gildenblat, X. Li, H. Wang, A. Jha, R. van Langevelde, G. D. J. Smit, A. J. Scholden and D. B. M. Klaassen, “PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation,” IEEE Transaction on Electron Devices, vol. 53, no. 9, pp. 1979–1993, September 2006.CrossRefGoogle Scholar
  13. 13.
    C. Mallikarjun and K. N. Bhat, “Numerical and Charge Sheet Models for Thin-Film SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 37, no. 9, pp. 2039–2051, September 1990.CrossRefGoogle Scholar
  14. 14.
    A. Ortiz-Conde, F. J. Garcia Sanchez, P. E. Schmit and A. Sa-Neto, “The Nonequilibrium Inversion Layer Charge of the Thin-Film SOI MOSFET,” IEEE Transaction on Electron Devices, vol. 36, no. 9, pp. 1651–1656, September 1989.CrossRefGoogle Scholar
  15. 15.
    H. Lu and Y. Taur, “An Analytic Potential Model for Symmetric and Asymmetric DG MOSFETs,” IEEE Transaction on Electron Devices, vol. 53, no. 5, pp. 1161–1168, May 2006.CrossRefGoogle Scholar
  16. 16.
    W. Z. Shangguan, X. Zhou, K. Chandrasekaran, Z. Zhu, S. C. Rustagi, S. B. Chiah and G. H. See, “Surface-Potential Solution for Generic Undoped MOSFETs with Two Gates,” IEEE Transaction on Electron Devices, vol. 54, no. 1, pp. 169–172, January 2007.CrossRefGoogle Scholar
  17. 17.
    X. Shi and M. Wong, “Analytical Solutions to the One-Dimensional Oxide-Silicon-Oxide System,” IEEE Transaction on Electron Devices, vol. 50, no. 8, pp. 1783–1800, August 2003.Google Scholar
  18. 18.
    A. Ortiz-Conde, F. J. Garcia-Sanchez, J. Muci, S. Malobabic and J. J. Liou, “A Review of Core Compact Models for Undoped Double Gate SOI MOSFETs,” IEEE Transaction on Electron Devices, vol. 54, no. 1, pp. 131–140, January 2007.CrossRefGoogle Scholar
  19. 19.
    Z. Zhu, X. Zhou, K. Chandrasekara, S. Rustagi and G. H. See, “Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors,” Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2067–2072, April 2007.CrossRefGoogle Scholar
  20. 20.
    K. Kim, J. G. Fossum and C.-T. Chuang, “Process/physics- based thershold voltage model for nano-scaled double-gate devices,” International Journal of Electronics, vol. 91, no. 3, pp. 139–148, March 2004.CrossRefGoogle Scholar
  21. 21.
    L. Ge and J. G. Fossum, “Analytical Modeling of Quantization and Volume Inversion in Thin Si-Film DG MOSFETs,” IEEE Transaction on Electron Devices, vol. 49, no. 2, pp. 287–294, February 2002.CrossRefGoogle Scholar
  22. 22.
    J. Fossum and V. P. Trivedi, “UFDG, and Nanoscale FinFET-CMOS Design and Performance Projections,” in Proceeding of IEEE International Conference on Integrated Circuit and Technology, pp. 179–182, Austin, TX,May 9–11, 2005.Google Scholar
  23. 23.
    J. Fossum, “Recent Upgrades and Applications of UFDG,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 674–679, Boston, MA, May 9–11, 2006.Google Scholar
  24. 24.
    G. Pei, W. Ni, A. V. Kammula, B. A. Minch and E. C. C. Kan, “A Physical Compact Model of DG MOSFET for Mixed-Signal Circuit Applications — Part1: Model Description,” IEEE Transaction on Electron Devices, vol. 50, no. 10, pp. 2135–2143, October 2003.CrossRefGoogle Scholar
  25. 25.
    G. Pei, W. Ni, A. V. Kammula, B. A. Minch and E. C. C. Kan, “A Physical Compact Model of DG MOSFET for Mixed-Signal Circuit Applications — Part2: Parameter Extraction,” IEEE Transaction on Electron Devices, vol. 50, no. 10, pp. 2144–2153, October 2003.CrossRefGoogle Scholar
  26. 26.
    G. Pei and E. C. C. Kan, “Independently Driven DG MOSFETs for Mixed-Signal Circuits — Part1: Quasi-Static and Nonquasi-Static Channel Coupling,” IEEE Transaction on Electron Devices, vol. 51, no. 12, pp. 2086–2093, December 2004.CrossRefGoogle Scholar
  27. 27.
    H. K. Lim and J. G. Fossum, “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET's,” IEEE Transaction on Electron Devices, vol. 30, no. 10, pp. 1244–1251, October 1983.CrossRefGoogle Scholar
  28. 28.
    M. Reyboz, O. Rozeau, T. Poiroux, P. Martin M. Cavelier and J. Jomaah, “Explicit Short Channel Compact Model of Independent Double Gate MOSFET,” in Proceeding of Workshop on Compact Modeling, Nanotech 2007, pp. 578–581, Santa Clara, CA, May 20–24, 2007.Google Scholar
  29. 29.
    Y. Cheng and C. Hu, “MOSFET Modeling & BSIM3 Users Guide,” Kluwer,Dordrecht, 1999.Google Scholar
  30. 30.
    Z. Lu and J.G. Fossum, “Short-Channel Effects in Independent-Gate FinFETs,” IEEE Electron Device Letters, vol. 28, no. 2, pp. 145–147, February 2007.CrossRefGoogle Scholar
  31. 31.
    M. Reyboz, O. Rozeau, T. Poiroux, P. Martin, J. Jomaah, “An Explicit Analytical Charge-Based Model of Undoped Independent Double Gate MOSFET,” Solid-State Electronics, vol. 50, no. 7, pp. 1276–1282, July 2006.CrossRefGoogle Scholar
  32. 32.
    J.-P. Colinge, “Subthreshold Slope of Thin-Film SOI MOSFET's,” IEEE Electron Device Letters, vol. 7, no. 4, pp. 244–246, April 1986.CrossRefGoogle Scholar
  33. 33.
    C. Lombardi, S. Manzini, A. Saporito and M. Vanzini, “A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices,” IEEE Transaction on Computer-Aided Design, vol. 7, no. 11, pp. 1164–1171, November 1988.CrossRefGoogle Scholar
  34. 34.
    M. Reyboz, P. Martin, O. Rozeau and T. Poiroux, “Improved Carrier Mobility in Compact Model of Independent Double Gate MOSFET,” in Proceeding of Workshop on Compact Modeling, Nanotech 2008, Boston, MA, June 1–5, 2008.Google Scholar
  35. 35.
    Y. Tsividis, “Operation and Modeling of MOSFET,” WCB/McGraw-Hill, Second Edition, 1989.Google Scholar
  36. 36.
    S. Veeraraghavan and J. G. Fossum, “A Physical Short-Channel Model for the Thin-Film SOI MOSFET Applicable to Device and Circuit CAD,” IEEE Transaction on Electron Devices, vol. 35, no. 11, pp. 1866–1875, November 1988.CrossRefGoogle Scholar
  37. 37.
    S. Veeraraghavan and J. G. Fossum, “Short-Channel effects in SOI MOSFETs,” IEEE Transaction on Electron Devices, vol. 36, no. 3, pp. 522–528, March 1989.CrossRefGoogle Scholar
  38. 38.
    K. K. Young, “Short-Channel Effect in Fully Depleted SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 36, no. 2, pp. 399–402, February 1989.CrossRefGoogle Scholar
  39. 39.
    K. Suzuki and T. Sugii, “Analytical Models for n+-p+ Double-Gate SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 42, no. 12, pp. 1940–1948, November 1995.CrossRefGoogle Scholar
  40. 40.
    K. Suzuki, Y. Tosaka, and T. Sugii, “Analytical Threshold Voltage Model for Short Channel n+-p+ Double-Gate SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 43, no. 5, pp. 1166–1168, July 1996.CrossRefGoogle Scholar
  41. 41.
    K. Suzuki, “Short Channel MOSFET Model Using a Universal Channel Depletion Width Parameter,” IEEE Transaction on Electron Devices, vol. 47, no. 6, pp. 1202–1208, June 2000.CrossRefGoogle Scholar
  42. 42.
    K. Suzuki and S. Pidin, “Short Channel Single-Gate SOI MOSFET Model,” IEEE Transaction on Electron Devices, vol. 50, no. 5, pp. 1297–1305, May 2003.CrossRefGoogle Scholar
  43. 43.
    M. J. Kumar and A. Chaudhry, “Two-Dimensional Analytical Modeling of Fully Depleted DMG SOI MOSFET and Evidence for Diminished SCEs,” IEEE Transaction on Electron Devices, vol. 51, no. 4, pp. 569–574, April 2004.CrossRefGoogle Scholar
  44. 44.
    K. Nehari, J.-L. Autran, S. Harrison, O. Tintori and T. Skotnicki, “Compact Modeling of Threshold Voltage in Double-Gate MOSFET including quantum mechanical and short channel effects,” in Proceeding of Workshop on Compact Modeling, Nanotech 2005, Anaheim, CA, May 8–12, 2005.Google Scholar
  45. 45.
    D. Munteanu, J.-L. Autran and S. Harrison, “Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivity gate dielectrics,” Journal of Non-Crystalline Solids 2005, vol. 351, no. 21–23, pp. 1911–1918, July 2005.CrossRefGoogle Scholar
  46. 46.
    D. Munteanu, J.-L. Autran, X. Loussier, S. Harrison, R. Cerutti and T. Skotnicki, “Quantum Short-Channel Compact Modelling of Drain-Current in Double-Gate MOSFET,” in Proceeding of the 35th European Solid-State Device Research Conference, ESSDERC 2005, Grenoble, France, pp. 137–140, September 12–16 2005.Google Scholar
  47. 47.
    J. Osthaug and T. A. Fjeldly, “Closed-form 2D modelling of sub-100 nm MOSFETs in the sub-threshold regime,” Journal of Telecommunications and Information Technology, vol. 1/2004, pp. 70–79, January 2004.Google Scholar
  48. 48.
    S. Kolberg and T. A. Fjeldly, “2D Modeling of Nanoscale Double Gate SOI MOSFETs Using Conformal Mapping,” 21st Nordic semiconductor Meeting, Sundvolden, Norway, August 18–19 2005.Google Scholar
  49. 49.
    T.A. Fjeldly, S. Kolberg and B. Iñíguez, “Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal mapping Techniques,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 668–673, Boston, MA, May 9–11, 2006.Google Scholar
  50. 50.
    S. P. Chin and C. Y. Wu, “A New Two-Dimensional Model for the Potential Distribution of Short Gate-Length MESFET's and Its Applications,” IEEE Transaction on Electron Devices, vol. 39, no. 8, pp. 1928–1937, August 1992.CrossRefGoogle Scholar
  51. 51.
    J. Y. Guo and C. Y. Wu, “A New 2D Analytic Threshold-Voltage Model for Fully Depleted Short-Channel SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 40, no. 9, pp. 1653–1661, September 1993.CrossRefGoogle Scholar
  52. 52.
    H. Van Meyer and K. De Meyer, “A 2-D Analytical Threshold Voltage Model for Fully-Depleted SOI MOSFETs With Halos or Pockets,” IEEE Transaction on Electron Devices, vol. 48, no. 10, pp. 2292–2302, October 2001.CrossRefGoogle Scholar
  53. 53.
    J. C. S. Woo, K. W. Terrill and P. K. Vasudev, “Two-Dimensional Analytic Modeling of Very Thin SOI MOSFET's,” IEEE Transaction on Electron Devices, vol. 37, no. 9, pp. 1999–2006, September 1990.CrossRefGoogle Scholar
  54. 54.
    D. J. Frank, Y. Taur and H. S. P. Wong, “Generalized Scale length for Two-Dimensional Effects in MOSFET's,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 385–387, October 1998.CrossRefGoogle Scholar
  55. 55.
    D. Monroe and J. M. Hergenrother, “Evanescent-Mode Analysis of Short Channel Effects in Fully Depleted SOI and Related MOSFETs,” Proceeding of IEEE International SOI Conference, Stuart, FL, pp. 157–158, October 5–8 1998.Google Scholar
  56. 56.
    S. H. Oh, D. Monroe and J. M. Hergenrother, “Analytic Description of Short-Channel Effects in Fully Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs,” IEEE Electron Device Letters, vol. 21, no. 9, pp. 445–447, September 2000.CrossRefGoogle Scholar
  57. 57.
    G. Pei, V. Narayanan, Z. Liu and E. C. Kan, “3D Analytical Subthreshold and Quantum Mechanical Analyses of Double-Gate MOSFET,” in Proceeding of International Electron Devices Meeting, IEDM 2001, Washington, DC, pp. 103–106, December 2–5, 2001.Google Scholar
  58. 58.
    J. S. Park, S. Y. Lee, H. Shin and R. W. Dutton, “Analytical analysis of short-channel effects in MOSFETs for sub-100 nm technology,” IEEE Electronics Letters, vol. 38, no. 20, pp. 1222– 1223, September 2002.CrossRefGoogle Scholar
  59. 59.
    X. Liang and Y. Taur, “A 2-D Analytical Solution for SCEs in DG MOSFETs,” IEEE Transaction on Electron Devices, vol. 51, no. 9, pp. 1385–1391, September 2004.CrossRefGoogle Scholar
  60. 60.
    H. Lu, X. Liang, W. Wang and Y. Taur, “Compact Modeling of Short Channel Double-Gate MOSFETs,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 741–744, Boston, MA, May 9–11, 2006.Google Scholar
  61. 61.
    Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko and Y. C. Cheng, “Threshold Voltage Model for Deep-Submicrometer MOSFETs,” IEEE Transaction on Electron Devices, vol. 40, no. 1, pp. 86–95, January 1993.CrossRefGoogle Scholar
  62. 62.
    Y. A. El-Mansy et A. R. Boothroyd, “A Simple Two-Dimensional Model for IGFET Operation in the Saturation Region,” IEEE Transaction on Electron Devices, vol. 24, no. 3, pp. 254–262, March 1977.CrossRefGoogle Scholar
  63. 63.
    T.-E. Chang, C. Huang and T. Wang, “Mechanisms of Interface Trap-Induced Drain Leakage Current in Off-State n-MOSFET's,” IEEE Transaction on Electron Devices, vol. 42, no. 4, pp. 738–743, April 1995.CrossRefGoogle Scholar
  64. 64.
    Y.-K. Choi, D. Ha, T.-J. King and J. Bokor, “Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs,” Journal of Applied Physics, vol. 42, no. 4B, pp. 2073–2076, April 2003.Google Scholar
  65. 65.
    S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs,” IEEE Electronics Letters, vol. 18, no. 5, pp. 209–211, May 1997.CrossRefGoogle Scholar
  66. 66.
    W.-K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar and A. F. Tasch Jr., “Modeling Gate Leakage Current in nMOS Structures Due to Tunneling Through an Ultra-Thin Oxide,” Solid State Electronics, vol. 42, no. 6, pp. 997–1006, June 1998.CrossRefGoogle Scholar
  67. 67.
    C.-H. Choi, K.-H. Oh, J.-S. Goo, Z. Yu, and R. W. Dutton, “Direct tunneling current model for circuit simulation,” Proceeding of International Electron Devices Meeting, IEDM 1999, Washington, DC, pp. 735–738, December 5–8, 1999.Google Scholar
  68. 68.
    W.-C. Lee and C. Hu, “Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling,” IEEE Transaction on Electron Devices, vol. 48, no. 7, pp. 1366–1373, June 2001.CrossRefGoogle Scholar
  69. 69.
    W.-K. Shih, R. Rios, P. Packan, K. Mistry and T. Abbott., “A General Partition Scheme for Gate Leakage Current Suitable for MOSFET Compact Models,” Proceeding of International Electron Devices Meeting, IEDM 2001, Washington, DC, pp. 293–296, December 2–5 2001.Google Scholar
  70. 70.
    K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu and C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” Proceeding of International Electron Devices Meeting, IEDM 2000, San Francisco, CA, pp. 815–818, December 10–13, 2000.Google Scholar

Copyright information

© Springer Science + Business Media B.V. 2009

Authors and Affiliations

  • Marina Reyboz
    • 1
  • Olivier Rozeau
    • 1
  • Thierry Poiroux
    • 1
  1. 1.CEA-LETI MinatecGrenoble Cedex 9France

Personalised recommendations