A Complete Biopotential Acquisition ASIC

Another power consuming block of an EEG acquisition systems is the ADC. Therefore, the power autonomy of the biopotential acquisition systems can be further improved, if an on-chip low-power ADC is included together with the analog readout front-end. This Chapter describes a complete EEG Acquisition ASIC, where the outputs of the analog readout front-ends can be digitized using the on-chip low-power ADC. This eliminates the use of an external ADC that not only improves the power dissipation of the EEG acquisition system but also can shrink the system size.

Moreover, a new ACCIA architecture is introduced that improves the NEF of the presented ACCIA in Chap. 4 and eliminates the need for external passives for implementing HPF characteristics. Thus, both the power autonomy and the size of the EEG acquisition system can be further improved. In addition to the acquisition mode, the ASIC has impedance measurement and calibration modes. During the impedance measurement mode, the ASIC is configured such that is can measure the impedance of the biopotential electrodes, where as, during the calibration mode the gain mismatch of the readout front-end channels can be calculated.

The organization of the Chapter is as follows; Sect. 5.2 presents the architecture and the functional block diagram of the EEG acquisition ASIC. Section 5.3 describes how the bias currents and the voltages for the building blocks of the ASIC are generated. Section 5.4 describes the Class-AB buffer architecture of the ASIC that is used to buffer the output voltage of the front-end channels and the reference voltage of the ADC. Section 5.2 presents the proposed ACCIA architecture that improves the NEF of the ACCIA of Sect. 4.2, and eliminates the need for external passives. Section 5.6 and Sect. 5.7 describes the CSF stage, and the programmable gain stage, respectively, and Sect. 5.8 presents the measured performance of the readout front-end channels. Section 5.9 describes the design of the relaxation oscillator that generates the operating clock of the ADC. Section 5.10 describes the design of the 11-bit SAR-ADC of the ASIC. Section 5.11 describes the impedance measurement and calibration modes of the ASIC. Finally, Sect. 5.14 states the conclusions of this Chapter.