Reliability-Oriented Place and Route Algorithm

In general, the commonly used design-flow to map designs onto a SRAM-based FPGA consist of three phases. In the first phase, a synthesizer is used to transform a circuit model coded in a hardware description language into an RTL design. In the second phase a technology mapper transforms the RTL design into a gate-level model composed of look-up tables (LUTs) and flip flops (FFs) and it binds them to the FPGA’s resources (producing the technology-mapped design). In the third phase, the technology mapped design is physically implemented on the FPGA by the place and route algorithm.